[Mips] In LowerShift*Parts, xor with bits-1 instead of -1.

[topperc]

If we start with an i128 shift, the initial shift amount would usually have zeros in bit 8 and above. xoring the shift amount with -1 will set those upper bits to 1. If DAGCombiner is able to prove those bits are now 1, then the shift that uses the xor will be replaced with undef. Which we don't want.

Reduce the xor constant to VT.bits-1 where VT is half the size of the larger shift type. This avoids toggling the upper bits. The hardware shift instruction only uses the lower bits of the shift amount. I assume the code used NOT because the hardware doesn't use the upper bits, but that isn't compatible with the LLVM poison semantics.

Fixes #71142.

I don't know who can review Mips anymore so I'm just adding mostly people who know about SelectionDAG and/or lowering shift parts.

[RKSimon]

FTR #71154 does something similar but this looks more complete

[RKSimon]

LGTM (with a couple of minors)

[RKSimon]

consistent style: (xor (VT.bits-1), shamt)

[RKSimon]

consistent style: (xor (VT.bits-1), shamt)

[topperc]

There's another bug in this code that neither patch addresses.

I believe this violates the boolean rules. ISD::SELECT should only receive 0/1 as a condition. There needs to be a setcc here.

  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,                      
                             DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 
  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,                                    
                   DAG.getConstant(0, DL, VT), ShiftLeftLo); 

[yingopq]

There's another bug in this code that neither patch addresses.

I believe this violates the boolean rules. ISD::SELECT should only receive 0/1 as a condition. There needs to be a setcc here.

  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,                      
                             DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32)); 
  Lo = DAG.getNode(ISD::SELECT, DL, VT, Cond,                                    
                   DAG.getConstant(0, DL, VT), ShiftLeftLo); 

@topperc There has a question about shift number 129, now we deal with it as shift number 1 and the result of shl i128 %a, %b was ffffffffffffffff fffffffffffffffe.
If we add a setcc like the following diff, the above result was fffffffffffffffe 0000000000000000 like RISCV RISCVTargetLowering::lowerShiftLeftParts. Whether we're going to change the behavior of the shift number 129?

+//  SDValue Cond = DAG.getNode(ISD::AND, DL, MVT::i32, Shamt,
+//                             DAG.getConstant(VT.getSizeInBits(), DL, MVT::i32));
+
+  SDValue MinusXLen = DAG.getConstant(-(int)VT.getSizeInBits(), DL, MVT::i32);
+  SDValue ShamtMinusXLen = DAG.getNode(ISD::ADD, DL, MVT::i32, Shamt, MinusXLen);
+  SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
+  SDValue CC = DAG.getSetCC(DL, MVT::i32, ShamtMinusXLen, Zero, ISD::SETLT);
+  Lo = DAG.getNode(ISD::SELECT, DL, VT, CC, ShiftLeftLo, DAG.getConstant(0, DL, VT));
+  Hi = DAG.getNode(ISD::SELECT, DL, VT, CC, Or, ShiftLeftLo);