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Add the tablegen mechanism to lower intrinsics to DXIL ops with extra enum arguments. #112974

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adam-yang opened this issue Oct 18, 2024 · 0 comments · Fixed by #111884 or #114349
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backend:DirectX HLSL HLSL Language Support

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@adam-yang
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adam-yang commented Oct 18, 2024

Some DXIL ops are generic operations that take additional enums to specify the actual type of operation. Here's a quick list of operations that fit the pattern:

WaveActiveOp          _, WaveOpKind, SignedOpKind
WaveActiveBit         _, WaveBitOpKind
WavePrefixOp          _, WaveOpKind, SignedOpKind
QuadOp                _, QuadOpKind
WaveMultiPrefixOp     _, _, _, _, _, WaveMultiPrefixOpKind, SignedOpKind
QuadVote              _, _, QuadVoteOpKind
Barrier               BarrierMode

AtomicBinOp           _, AtomicBinOpCode, _, _, _, _
WaveMatrix_ScalarOp   _, WaveMatrixScalarOpCode, _

We need a tablegen solution to easily declare:

  • What intrinsic should lower to this DXIL op
  • What arguments should come from the original intrinsic and what order should they be
  • What additional enum arguments should the specific intrinsic map to.
@adam-yang adam-yang added backend:DirectX HLSL HLSL Language Support labels Oct 18, 2024
@adam-yang adam-yang self-assigned this Oct 18, 2024
@adam-yang adam-yang moved this to Active in HLSL Support Oct 18, 2024
@damyanp damyanp moved this from Active to Needs Review in HLSL Support Oct 21, 2024
adam-yang added a commit that referenced this issue Oct 29, 2024
fixes #112974
partially fixes #70103

### Changes
- Added new tablegen based way of lowering dx intrinsics to DXIL ops.
- Added int_dx_group_memory_barrier_with_group_sync intrinsic in
IntrinsicsDirectX.td
- Added expansion for int_dx_group_memory_barrier_with_group_sync in
DXILIntrinsicExpansion.cpp`
- Added DXIL backend test case

### Related PRs
* [[clang][HLSL] Add GroupMemoryBarrierWithGroupSync intrinsic
#111883](#111883)
* [[SPIRV] Add GroupMemoryBarrierWithGroupSync intrinsic
#111888](#111888)
@github-project-automation github-project-automation bot moved this from Needs Review to Closed in HLSL Support Oct 29, 2024
@adam-yang adam-yang moved this from Closed to Needs Review in HLSL Support Oct 31, 2024
@damyanp damyanp reopened this Oct 31, 2024
NoumanAmir657 pushed a commit to NoumanAmir657/llvm-project that referenced this issue Nov 4, 2024
fixes llvm#112974
partially fixes llvm#70103

### Changes
- Added new tablegen based way of lowering dx intrinsics to DXIL ops.
- Added int_dx_group_memory_barrier_with_group_sync intrinsic in
IntrinsicsDirectX.td
- Added expansion for int_dx_group_memory_barrier_with_group_sync in
DXILIntrinsicExpansion.cpp`
- Added DXIL backend test case

### Related PRs
* [[clang][HLSL] Add GroupMemoryBarrierWithGroupSync intrinsic
llvm#111883](llvm#111883)
* [[SPIRV] Add GroupMemoryBarrierWithGroupSync intrinsic
llvm#111888](llvm#111888)
@github-project-automation github-project-automation bot moved this from Needs Review to Closed in HLSL Support Dec 2, 2024
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backend:DirectX HLSL HLSL Language Support
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