fixup! [SPARC] Support reserving arbitrary general purpose registers

llvm · Jan 21, 2024 · a7e35ea · a7e35ea
1 parent eb8204d
commit a7e35ea
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Showing 4 changed files with 21 additions and 35 deletions.
diff --git a/llvm/lib/Target/Sparc/Sparc.td b/llvm/lib/Target/Sparc/Sparc.td
@@ -74,16 +74,16 @@ include "LeonFeatures.td"
 
 //==== Register allocation tweaks needed by some low-level software
 foreach i = 1 ... 7  in
-    def FeatureReserveG#i : SubtargetFeature<"reserve-g"#i, "ReserveGRegister["#i#"]", "true",
+    def FeatureReserveG#i : SubtargetFeature<"reserve-g"#i, "ReserveRegister["#i#" + SP::G0 - SP::G0]", "true",
                                              "Reserve G"#i#", making it unavailable as a GPR">;
 foreach i = 0 ... 5 in
-    def FeatureReserveO#i : SubtargetFeature<"reserve-o"#i, "ReserveORegister["#i#"]", "true",
+    def FeatureReserveO#i : SubtargetFeature<"reserve-o"#i, "ReserveRegister["#i#" + SP::O0 - SP::G0]", "true",
                                              "Reserve O"#i#", making it unavailable as a GPR">;
 foreach i = 0 ... 7 in
-    def FeatureReserveL#i : SubtargetFeature<"reserve-l"#i, "ReserveLRegister["#i#"]", "true",
+    def FeatureReserveL#i : SubtargetFeature<"reserve-l"#i, "ReserveRegister["#i#" + SP::L0 - SP::G0]", "true",
                                              "Reserve L"#i#", making it unavailable as a GPR">;
 foreach i = 0 ... 5 in
-    def FeatureReserveI#i : SubtargetFeature<"reserve-i"#i, "ReserveIRegister["#i#"]", "true",
+    def FeatureReserveI#i : SubtargetFeature<"reserve-i"#i, "ReserveRegister["#i#" + SP::I0 - SP::G0]", "true",
                                              "Reserve I"#i#", making it unavailable as a GPR">;
 
 //===----------------------------------------------------------------------===//

diff --git a/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp b/llvm/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -96,26 +96,13 @@ BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   for (unsigned n = 0; n < 31; n++)
     Reserved.set(SP::ASR1 + n);
 
-  for (size_t i = 0; i < SP::IntRegsRegClass.getNumRegs() / 4; ++i) {
-    // Mark both single register and register pairs.
-    if (MF.getSubtarget<SparcSubtarget>().isGRegisterReserved(i)) {
-      Reserved.set(SP::G0 + i);
-      Reserved.set(SP::G0_G1 + i / 2);
-    }
-    if (MF.getSubtarget<SparcSubtarget>().isORegisterReserved(i)) {
-      Reserved.set(SP::O0 + i);
-      Reserved.set(SP::O0_O1 + i / 2);
-    }
-    if (MF.getSubtarget<SparcSubtarget>().isLRegisterReserved(i)) {
-      Reserved.set(SP::L0 + i);
-      Reserved.set(SP::L0_L1 + i / 2);
-    }
-    if (MF.getSubtarget<SparcSubtarget>().isIRegisterReserved(i)) {
-      Reserved.set(SP::I0 + i);
-      Reserved.set(SP::I0_I1 + i / 2);
-    }
+  for (TargetRegisterClass::iterator i = SP::IntRegsRegClass.begin();
+       i != SP::IntRegsRegClass.end(); ++i) {
+    if (MF.getSubtarget<SparcSubtarget>().isRegisterReserved(*i))
+      markSuperRegs(Reserved, *i);
   }
 
+  assert(checkAllSuperRegsMarked(Reserved));
   return Reserved;
 }
 

diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.cpp b/llvm/lib/Target/Sparc/SparcSubtarget.cpp
@@ -50,10 +50,7 @@ SparcSubtarget::SparcSubtarget(const StringRef &CPU, const StringRef &TuneCPU,
                                const StringRef &FS, const TargetMachine &TM,
                                bool is64Bit)
     : SparcGenSubtargetInfo(TM.getTargetTriple(), CPU, TuneCPU, FS),
-      ReserveGRegister(SP::IntRegsRegClass.getNumRegs() / 4),
-      ReserveORegister(SP::IntRegsRegClass.getNumRegs() / 4),
-      ReserveLRegister(SP::IntRegsRegClass.getNumRegs() / 4),
-      ReserveIRegister(SP::IntRegsRegClass.getNumRegs() / 4),
+      ReserveRegister(SP::IntRegsRegClass.getNumRegs()),
       TargetTriple(TM.getTargetTriple()), Is64Bit(is64Bit),
       InstrInfo(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
       TLInfo(TM, *this), FrameLowering(*this) {}

diff --git a/llvm/lib/Target/Sparc/SparcSubtarget.h b/llvm/lib/Target/Sparc/SparcSubtarget.h
@@ -13,12 +13,14 @@
 #ifndef LLVM_LIB_TARGET_SPARC_SPARCSUBTARGET_H
 #define LLVM_LIB_TARGET_SPARC_SPARCSUBTARGET_H
 
+#include "MCTargetDesc/SparcMCTargetDesc.h"
 #include "SparcFrameLowering.h"
 #include "SparcISelLowering.h"
 #include "SparcInstrInfo.h"
 #include "llvm/CodeGen/SelectionDAGTargetInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/IR/DataLayout.h"
+#include "llvm/Support/ErrorHandling.h"
 #include "llvm/TargetParser/Triple.h"
 #include <string>
 
@@ -29,11 +31,9 @@ namespace llvm {
 class StringRef;
 
 class SparcSubtarget : public SparcGenSubtargetInfo {
-  // Reserve*Register[i] - *#i is not available as a general purpose register.
-  BitVector ReserveGRegister;
-  BitVector ReserveORegister;
-  BitVector ReserveLRegister;
-  BitVector ReserveIRegister;
+  // ReserveRegister[i] - Register #i is not available as a general purpose
+  // register.
+  BitVector ReserveRegister;
 
   Triple TargetTriple;
   virtual void anchor();
@@ -88,10 +88,12 @@ class SparcSubtarget : public SparcGenSubtargetInfo {
     return is64Bit() ? 2047 : 0;
   }
 
-  bool isGRegisterReserved(size_t i) const { return ReserveGRegister[i]; }
-  bool isORegisterReserved(size_t i) const { return ReserveORegister[i]; }
-  bool isLRegisterReserved(size_t i) const { return ReserveLRegister[i]; }
-  bool isIRegisterReserved(size_t i) const { return ReserveIRegister[i]; }
+  bool isRegisterReserved(MCPhysReg PhysReg) const {
+    if (PhysReg >= SP::G0 && PhysReg <= SP::O7)
+      return ReserveRegister[PhysReg - SP::G0];
+
+    llvm_unreachable("Invalid physical register passed!");
+  }
 
   /// Given a actual stack size as determined by FrameInfo, this function
   /// returns adjusted framesize which includes space for register window