phy: switch to bus

switch to SDR/DDRTristateBus and SDROutputBus.

Signed-off-by: Fin Maaß <[email protected]>

litespi/phy/generic_ddr.py

@@ -15,7 +15,7 @@
 
 from litex.soc.interconnect import stream
 
-from litex.build.io import DDRTristate, SDROutput
+from litex.build.io import DDRTristateBus, SDROutputBus
 
 # LiteSPI DDR PHY Core -----------------------------------------------------------------------------
 
@@ -77,26 +77,23 @@ def __init__(self, pads, flash, cs_delay, extra_latency=0):
         cs_enable = Signal()
         self.comb += cs_timer.wait.eq(self.cs != 0)
         self.comb += cs_enable.eq(cs_timer.done)
-        for i in range(len(pads.cs_n)):
-            self.specials += SDROutput(
-                i = ~(cs_enable & self.cs[i]),
-                o = pads.cs_n[i]
-            )
-
-        # I/Os.
-        data_bits = 32
+        cs_n = Signal().like(pads.cs_n)
+        self.comb += cs_n.eq(~(Replicate(cs_enable, len(pads.cs_n)) & self.cs))
+        self.specials += SDROutputBus(
+            i = cs_n,
+            o = pads.cs_n
+        )
 
         dq_o  = Array([Signal(len(pads.dq)) for _ in range(2)])
         dq_i  = Array([Signal(len(pads.dq)) for _ in range(2)])
         dq_oe = Array([Signal(len(pads.dq)) for _ in range(2)])
 
-        for i in range(len(pads.dq)):
-            self.specials += DDRTristate(
-                io  = pads.dq[i],
-                o1  =  dq_o[0][i],  o2 =  dq_o[1][i],
-                oe1 = dq_oe[0][i], oe2 = dq_oe[1][i],
-                i1  =  dq_i[0][i],  i2 =  dq_i[1][i]
-            )
+        self.specials += DDRTristateBus(
+            io  = pads.dq,
+            o1  =  dq_o[0],  o2 =  dq_o[1],
+            oe1 = dq_oe[0], oe2 = dq_oe[1],
+            i1  =  dq_i[0],  i2 =  dq_i[1]
+        )
 
         # Data Shift Registers.
         sr_cnt       = Signal(8, reset_less=True)

litespi/phy/generic_sdr.py

@@ -17,7 +17,7 @@
 from litex.soc.interconnect import stream
 from litex.soc.interconnect.csr import *
 
-from litex.build.io import SDROutput, SDRInput, SDRTristate
+from litex.build.io import SDROutput, SDRInput, SDRTristateBus, SDROutputBus
 
 # LiteSPI PHY Core ---------------------------------------------------------------------------------
 
@@ -96,11 +96,12 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
         cs_enable = Signal()
         self.comb += cs_timer.wait.eq(self.cs != 0)
         self.comb += cs_enable.eq(cs_timer.done)
-        for i in range(len(pads.cs_n)):
-            self.specials += SDROutput(
-                i = ~(cs_enable & self.cs[i]),
-                o = pads.cs_n[i]
-            )
+        cs_n = Signal().like(pads.cs_n)
+        self.comb += cs_n.eq(~(Replicate(cs_enable, len(pads.cs_n)) & self.cs))
+        self.specials += SDROutputBus(
+            i = cs_n,
+            o = pads.cs_n
+        )
 
         if hasattr(pads, "mosi"):
             dq_o  = Signal()
@@ -118,12 +119,11 @@ def __init__(self, pads, flash, device, clock_domain, default_divisor, cs_delay)
             dq_o  = Signal().like(pads.dq)
             dq_i  = Signal().like(pads.dq)
             dq_oe = Signal().like(pads.dq)
-            for i in range(len(pads.dq)):
-                self.specials += SDRTristate(
-                    io = pads.dq[i],
-                    o  = dq_o[i],
-                    oe = dq_oe[i],
-                    i  = dq_i[i],
+            self.specials += SDRTristateBus(
+                    io = pads.dq,
+                    o  = dq_o,
+                    oe = dq_oe,
+                    i  = dq_i,
                 )
 
         # Data Shift Registers.