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Implement a number of ARMv8 instructions #477

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TheGreatRambler opened this issue Jan 23, 2021 · 5 comments
Open

Implement a number of ARMv8 instructions #477

TheGreatRambler opened this issue Jan 23, 2021 · 5 comments

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@TheGreatRambler
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A number of instructions are unimplemented and cause my executable to be unable to be recompiled. These are the instructions + other instruction errors I got:

!NO-FUNCTION!
FCSEL_S_FLOATSEL
FCCMP_S_FLOATCCMP
FMIN_S_FLOATDP2
STR_D_LDST_IMMPRE
STP_D_LDSTPAIR_PRE
INS_ASIMDINS_IV_V
FCVTZS_32S_FLOAT2FIX
SCVTF_ASISDMISC_R
FSQRT_S_FLOATDP1
CRC32B_32C_DP_2SRC
FNMUL_S_FLOATDP2
STP_Q_LDSTPAIR_OFF (READ_OP (REG_128 Q6)) (READ_OP (REG_128 Q7))
(WRITE_OP (DOWORD_PTR (ADD (REG_64 SP) (SIGNED_IMM_64 0x60))))
STP_Q_LDSTPAIR_OFF (READ_OP (REG_128 Q4)) (READ_OP (REG_128 Q5))
(WRITE_OP (DOWORD_PTR (ADD (REG_64 SP) (SIGNED_IMM_64 0x40))))
STP_Q_LDSTPAIR_OFF (READ_OP (REG_128 Q2)) (READ_OP (REG_128 Q3))
(WRITE_OP (DOWORD_PTR (ADD (REG_64 SP) (SIGNED_IMM_64 0x20))))
STP_Q_LDSTPAIR_OFF (READ_OP (REG_128 Q0)) (READ_OP (REG_128 Q1))
(WRITE_OP (DOWORD_PTR (REG_64 SP)))
UCVTF_ASISDMISC_R
DUP_ASISDONE_ONLY
LD1_ASISDLSO_S1_1S
ST1_ASISDLSO_S1_1S
FMAX_S_FLOATDP2
FMINNM_S_FLOATDP2
(WRITE_OP (DOWORD_PTR (ADD (REG_64 X8) (SIGNED_IMM_64 0x2d0))))
STXR_SR32_LDSTEXCL
STR_S_LDST_IMMPOST
STP_Q_LDSTPAIR_OFF (READ_OP (REG_128 Q2)) (READ_OP (REG_128 Q1))
STP_Q_LDSTPAIR_OFF (READ_OP (REG_128 Q4)) (READ_OP (REG_128 Q2))
(WRITE_OP (DOWORD_PTR (ADD (REG_64 SP) (SIGNED_IMM_64 0x50))))
LD1R_ASISDLSO_R1
FMUL_ASIMDELEM_R_SD
DUP_ASIMDINS_DV_V
FMAXNM_S_FLOATDP2
FADD_ASIMDSAME_ONLY
STR_S_LDST_IMMPRE
FCVTZS_64S_FLOAT2INT (WRITE_OP (REG_64 X8)) (READ_OP (REG_32 S5))
FCVTZS_64S_FLOAT2INT (WRITE_OP (REG_64 X8)) (READ_OP (REG_32 S2))
FMUL_ASISDELEM_R_SD
STP_Q_LDSTPAIR_OFF (READ_OP (REG_128 Q1)) (READ_OP (REG_128 Q0))
(WRITE_OP (DOWORD_PTR (ADD (REG_64 X19) (SIGNED_IMM_64 0x20))))
STR_S_LDST_REGOFF
(WRITE_OP (DOWORD_PTR (ADD (REG_64 X19) (SIGNED_IMM_64 0x2d0))))
FABD_ASISDSAME_ONLY
(WRITE_OP (DOWORD_PTR (ADD (REG_64 SP) (SIGNED_IMM_64 0x30))))
(WRITE_OP (DOWORD_PTR (ADD (REG_64 X21) (SIGNED_IMM_64 0x180))))
(WRITE_OP (DOWORD_PTR (ADD (REG_64 X21) (SIGNED_IMM_64 0x1a0))))
FMUL_ASIMDSAME_ONLY
STP_Q_LDSTPAIR_OFF (READ_OP (REG_128 Q24)) (READ_OP (REG_128 Q25))
(WRITE_OP (DOWORD_PTR (ADD (REG_64 X17) (SIGNED_IMM_64 0xb0))))
FCVTZS_64S_FLOAT2INT (WRITE_OP (REG_64 X8)) (READ_OP (REG_32 S1))
(WRITE_OP (DOWORD_PTR (REG_64 X20)))
(WRITE_OP (DOWORD_PTR (ADD (REG_64 X19) (SIGNED_IMM_64 0x140))))
SSHLL_ASIMDSHF_L
STP_Q_LDSTPAIR_OFF (READ_OP (REG_128 Q0)) (READ_OP (REG_128 Q6))
(WRITE_OP (DOWORD_PTR (ADD (REG_64 SP) (SIGNED_IMM_64 0x10))))
(WRITE_OP (DOWORD_PTR (ADD (REG_64 X19) (SIGNED_IMM_64 0x180))))
(WRITE_OP (DOWORD_PTR (ADD (REG_64 X19) (SIGNED_IMM_64 0x1a0))))
(WRITE_OP (DOWORD_PTR (REG_64 X1)))
TRN2_ASIMDPERM_ONLY
STP_Q_LDSTPAIR_OFF (READ_OP (REG_128 Q16)) (READ_OP (REG_128 Q17))
STP_Q_LDSTPAIR_OFF (READ_OP (REG_128 Q1)) (READ_OP (REG_128 Q2))
STP_Q_LDSTPAIR_OFF (READ_OP (REG_128 Q17)) (READ_OP (REG_128 Q3))
(WRITE_OP (DOWORD_PTR (ADD (REG_64 X8) (SIGNED_IMM_64 0xc0))))
LD1_ASISDLSOP_S1_I1S
FCVTZS_64S_FLOAT2INT (WRITE_OP (REG_64 X8)) (READ_OP (REG_32 S0))
STP_Q_LDSTPAIR_OFF (READ_OP (REG_128 Q2)) (READ_OP (REG_128 Q0))

These are just the instructions:

FCSEL_S_FLOATSEL
FCCMP_S_FLOATCCMP
FMIN_S_FLOATDP2
STR_D_LDST_IMMPRE
STP_D_LDSTPAIR_PRE
INS_ASIMDINS_IV_V
FCVTZS_32S_FLOAT2FIX
SCVTF_ASISDMISC_R
FSQRT_S_FLOATDP1
CRC32B_32C_DP_2SRC
FNMUL_S_FLOATDP2
UCVTF_ASISDMISC_R
DUP_ASISDONE_ONLY
LD1_ASISDLSO_S1_1S
ST1_ASISDLSO_S1_1S
FMAX_S_FLOATDP2
FMINNM_S_FLOATDP2
STXR_SR32_LDSTEXCL
STR_S_LDST_IMMPOST
LD1R_ASISDLSO_R1
FMUL_ASIMDELEM_R_SD
DUP_ASIMDINS_DV_V
FMAXNM_S_FLOATDP2
FADD_ASIMDSAME_ONLY
STR_S_LDST_IMMPRE
FMUL_ASISDELEM_R_SD
STR_S_LDST_REGOFF
FABD_ASISDSAME_ONLY
FMUL_ASIMDSAME_ONLY
SSHLL_ASIMDSHF_L
TRN2_ASIMDPERM_ONLY
LD1_ASISDLSOP_S1_I1S
CLREX_BN_SYSTEM

And here they are without that end part there:

FCSEL
FCCMP
FMIN
STR
STP
INS
FCVTZS
SCVTF
FSQRT
CRC32B
FNMUL
UCVTF
DUP
LD1
ST1
FMAX
FMINNM
STXR
LD1R
FMUL
FMAXNM
FADD
FABD
SSHLL
TRN2
CLREX
STR
SCVTF
UCVTF
FCSEL
FSQRT
FMIN
FNMUL
FMAX
DUP
INS
STP
STXR
FCCMP

Note, I was just using regex to select these so if they aren't actually instructions, sorry, I don't know what to call them. These might be all the instructions I need but there might be more even with some of these implemented. Thanks for the great software though, I got surprisingly far. The full logs from around 5 minutes of execution can be found here
logs.txt

@TheGreatRambler
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I could implement these myself but I would appreciate guidance on where I could find the instructions needed to handle each of these, as analysing the source code makes it seem like most of what is happening is register manipulation, which I know nothing about.

@TheGreatRambler
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Does Pull 461 have some or all of these implemented?

@pgoodman
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No, that is for AArch32. Completely different encoding.

@pgoodman
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Some of the semantics may bear some similarity, though.

@TheGreatRambler
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Oh, right. I honestly don't know the difference between semantics and instructions, so I couldn't tell if it was useful

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