Verilog example
In this example we'll make a counter using four T-type flip-flops.
You can find resulting schematic and relevant files for this example in the directory netlist/examples/verilog/T_FF_example of your Lepton EDA repository.
The symbols used in this schematic have been generated by the utility named gmk_sym. It is not installed automatically if you build the Lepton EDA distribution, though you can use it if you build Lepton using the --enable-contrib option. In this case it will reside in the contrib/gmk_sym/ directory of your build. After building, you may open your examples/gmk_sym directory and yield e.g. your_build_directory/contrib/gmk_sym/gmk_sym negedge.txt > D_FF.sym to make the symbol you will use in your schematic. You can then edit it in lepton-schematic to make the symbol view better.
Other symbols used in the schematic are the part of the Lepton distribution. Check the gafrc file in the example directory in order to find how to use them in your schematic.
In order to simulate this schematic, proceed as follows.
Use verilog backend for netlist generation:
lepton-netlist -g verilog -o verilog_modules/RIPPLE_COUNT.v sch/verilog_rip_test.sch
Compile the test (use Icarus Verilog compiler for this):
iverilog -y verilog_modules/ -o dummy_test.out dummy_test.v
Generate an output VCD file with the result of simulation:
./dummy_test.out
Open the result vcd file in gtkwave and play with it:
gtkwave test.vcd
