Fix style

fault/system_verilog_target.py

@@ -60,7 +60,7 @@ def __init__(self, circuit, circuit_name=None, directory="build/",
 
         magma_opts: Options dictionary for `magma.compile` command
 
-        simulator: "ncsim" or "vcs"
+        simulator: "ncsim", "vcs", or "iverilog"
 
         timescale: Set the timescale for the verilog simulation
                    (default 1ns/1ns)
@@ -282,7 +282,7 @@ def run(self, actions):
 vcs -sverilog -full64 +v2k -timescale={self.timescale} -LDFLAGS -Wl,--no-as-needed  {test_bench_file} {self.verilog_file} {verilog_libraries}
 """  # nopep8
         elif self.simulator == "iverilog":
-            cmd = f"iverilog -o {self.circuit_name}_tb {test_bench_file} {self.verilog_file}"
+            cmd = f"iverilog -o {self.circuit_name}_tb {test_bench_file} {self.verilog_file}"  # noqa
         else:
             raise NotImplementedError(self.simulator)
 
@@ -292,4 +292,4 @@ def run(self, actions):
             print(f"Running command: {cmd}")
             assert not subprocess.call("./simv", cwd=self.directory, shell=True)
         elif self.simulator == "iverilog":
-            assert not subprocess.call(f"vvp -N {self.circuit_name}_tb", cwd=self.directory, shell=True)
+            assert not subprocess.call(f"vvp -N {self.circuit_name}_tb", cwd=self.directory, shell=True)  # noqa