Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Update x/sys and x/net modules to support Risc-V #1344

Merged
merged 1 commit into from
Jun 8, 2019

Conversation

carlosedp
Copy link
Contributor

Updating projects using libraries that were recently updated to support Risc-V.

Go upstream work is tracked on: golang/go#27532

Risc-V software support tracker on https://github.com/carlosedp/riscv-bringup

@codecov
Copy link

codecov bot commented May 31, 2019

Codecov Report

Merging #1344 into master will not change coverage.
The diff coverage is n/a.

Impacted file tree graph

@@           Coverage Diff           @@
##           master    #1344   +/-   ##
=======================================
  Coverage   84.39%   84.39%           
=======================================
  Files          27       27           
  Lines        2019     2019           
=======================================
  Hits         1704     1704           
  Misses        205      205           
  Partials      110      110

Continue to review full report at Codecov.

Legend - Click here to learn more
Δ = absolute <relative> (impact), ø = not affected, ? = missing data
Powered by Codecov. Last update fbb7286...a00a819. Read the comment docs.

@vishr vishr merged commit 530f768 into labstack:master Jun 8, 2019
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Labels
None yet
Projects
None yet
Development

Successfully merging this pull request may close these issues.

2 participants