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Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upst…
…ream-linus
Pull MIPS updates from Ralf Baechle:
"This has been sitting in -next for a while with no objections and all
MIPS defconfigs except one are building fine; that one platform got
broken by another patch in your tree and I'm going to submit a patch
separately.
- a handful of fixes that didn't make 3.11
- a few bits of Octeon 3 support with more to come for a later
release
- platform enhancements for Octeon, ath79, Lantiq, Netlogic and
Ralink SOCs
- a GPIO driver for the Octeon
- some dusting off of the DECstation code
- the usual dose of cleanups"
* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (65 commits)
MIPS: DMA: Fix BUG due to smp_processor_id() in preemptible code
MIPS: kexec: Fix random crashes while loading crashkernel
MIPS: kdump: Skip walking indirection page for crashkernels
MIPS: DECstation HRT calibration bug fixes
MIPS: Export copy_from_user_page() (needed by lustre)
MIPS: Add driver for the built-in PCI controller of the RT3883 SoC
MIPS: DMA: For BMIPS5000 cores flush region just like non-coherent R10000
MIPS: ralink: Add support for reset-controller API
MIPS: ralink: mt7620: Add cpu-feature-override header
MIPS: ralink: mt7620: Add spi clock definition
MIPS: ralink: mt7620: Add wdt clock definition
MIPS: ralink: mt7620: Improve clock frequency detection
MIPS: ralink: mt7620: This SoC has EHCI and OHCI hosts
MIPS: ralink: mt7620: Add verbose ram info
MIPS: ralink: Probe clocksources from OF
MIPS: ralink: Add support for systick timer found on newer ralink SoC
MIPS: ralink: Add support for periodic timer irq
MIPS: Netlogic: Built-in DTB for XLP2xx SoC boards
MIPS: Netlogic: Add support for USB on XLP2xx
MIPS: Netlogic: XLP2xx update for I2C controller
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Documentation/devicetree/bindings/pci/ralink,rt3883-pci.txt
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| * Mediatek/Ralink RT3883 PCI controller | ||
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| 1) Main node | ||
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| Required properties: | ||
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| - compatible: must be "ralink,rt3883-pci" | ||
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| - reg: specifies the physical base address of the controller and | ||
| the length of the memory mapped region. | ||
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| - #address-cells: specifies the number of cells needed to encode an | ||
| address. The value must be 1. | ||
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| - #size-cells: specifies the number of cells used to represent the size | ||
| of an address. The value must be 1. | ||
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| - ranges: specifies the translation between child address space and parent | ||
| address space | ||
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| Optional properties: | ||
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| - status: indicates the operational status of the device. | ||
| Value must be either "disabled" or "okay". | ||
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| 2) Child nodes | ||
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| The main node must have two child nodes which describes the built-in | ||
| interrupt controller and the PCI host bridge. | ||
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| a) Interrupt controller: | ||
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| Required properties: | ||
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| - interrupt-controller: identifies the node as an interrupt controller | ||
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| - #address-cells: specifies the number of cells needed to encode an | ||
| address. The value must be 0. As such, 'interrupt-map' nodes do not | ||
| have to specify a parent unit address. | ||
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| - #interrupt-cells: specifies the number of cells needed to encode an | ||
| interrupt source. The value must be 1. | ||
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| - interrupt-parent: the phandle for the interrupt controller that | ||
| services interrupts for this device. | ||
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| - interrupts: specifies the interrupt source of the parent interrupt | ||
| controller. The format of the interrupt specifier depends on the | ||
| parent interrupt controller. | ||
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| b) PCI host bridge: | ||
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| Required properties: | ||
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| - #address-cells: specifies the number of cells needed to encode an | ||
| address. The value must be 0. | ||
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| - #size-cells: specifies the number of cells used to represent the size | ||
| of an address. The value must be 2. | ||
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| - #interrupt-cells: specifies the number of cells needed to encode an | ||
| interrupt source. The value must be 1. | ||
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| - device_type: must be "pci" | ||
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| - bus-range: PCI bus numbers covered | ||
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| - ranges: specifies the ranges for the PCI memory and I/O regions | ||
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| - interrupt-map-mask, | ||
| - interrupt-map: standard PCI properties to define the mapping of the | ||
| PCI interface to interrupt numbers. | ||
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| The PCI host bridge node migh have additional sub-nodes representing | ||
| the onboard PCI devices/PCI slots. Each such sub-node must have the | ||
| following mandatory properties: | ||
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| - reg: used only for interrupt mapping, so only the first four bytes | ||
| are used to refer to the correct bus number and device number. | ||
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| - device_type: must be "pci" | ||
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| If a given sub-node represents a PCI bridge it must have following | ||
| mandatory properties as well: | ||
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| - #address-cells: must be set to <3> | ||
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| - #size-cells: must set to <2> | ||
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| - #interrupt-cells: must be set to <1> | ||
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| - interrupt-map-mask, | ||
| - interrupt-map: standard PCI properties to define the mapping of the | ||
| PCI interface to interrupt numbers. | ||
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| Besides the required properties the sub-nodes may have these optional | ||
| properties: | ||
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| - status: indicates the operational status of the sub-node. | ||
| Value must be either "disabled" or "okay". | ||
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| 3) Example: | ||
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| a) SoC specific dtsi file: | ||
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| pci@10140000 { | ||
| compatible = "ralink,rt3883-pci"; | ||
| reg = <0x10140000 0x20000>; | ||
| #address-cells = <1>; | ||
| #size-cells = <1>; | ||
| ranges; /* direct mapping */ | ||
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| status = "disabled"; | ||
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| pciintc: interrupt-controller { | ||
| interrupt-controller; | ||
| #address-cells = <0>; | ||
| #interrupt-cells = <1>; | ||
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| interrupt-parent = <&cpuintc>; | ||
| interrupts = <4>; | ||
| }; | ||
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| host-bridge { | ||
| #address-cells = <3>; | ||
| #size-cells = <2>; | ||
| #interrupt-cells = <1>; | ||
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| device_type = "pci"; | ||
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| bus-range = <0 255>; | ||
| ranges = < | ||
| 0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */ | ||
| 0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */ | ||
| >; | ||
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| interrupt-map-mask = <0xf800 0 0 7>; | ||
| interrupt-map = < | ||
| /* IDSEL 17 */ | ||
| 0x8800 0 0 1 &pciintc 18 | ||
| 0x8800 0 0 2 &pciintc 18 | ||
| 0x8800 0 0 3 &pciintc 18 | ||
| 0x8800 0 0 4 &pciintc 18 | ||
| /* IDSEL 18 */ | ||
| 0x9000 0 0 1 &pciintc 19 | ||
| 0x9000 0 0 2 &pciintc 19 | ||
| 0x9000 0 0 3 &pciintc 19 | ||
| 0x9000 0 0 4 &pciintc 19 | ||
| >; | ||
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| pci-bridge@1 { | ||
| reg = <0x0800 0 0 0 0>; | ||
| device_type = "pci"; | ||
| #interrupt-cells = <1>; | ||
| #address-cells = <3>; | ||
| #size-cells = <2>; | ||
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| interrupt-map-mask = <0x0 0 0 0>; | ||
| interrupt-map = <0x0 0 0 0 &pciintc 20>; | ||
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| status = "disabled"; | ||
| }; | ||
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| pci-slot@17 { | ||
| reg = <0x8800 0 0 0 0>; | ||
| device_type = "pci"; | ||
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| status = "disabled"; | ||
| }; | ||
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| pci-slot@18 { | ||
| reg = <0x9000 0 0 0 0>; | ||
| device_type = "pci"; | ||
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| status = "disabled"; | ||
| }; | ||
| }; | ||
| }; | ||
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| b) Board specific dts file: | ||
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| pci@10140000 { | ||
| status = "okay"; | ||
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| host-bridge { | ||
| pci-bridge@1 { | ||
| status = "okay"; | ||
| }; | ||
| }; | ||
| }; |
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