fix CASET and our SPIFR length argument and we get three rabbits!

kivikakk · Jun 6, 2024 · e9f8ef0 · e9f8ef0
1 parent d39feb7
commit e9f8ef0
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Showing 3 changed files with 28 additions and 15 deletions.
diff --git a/src/main/scala/ee/kivikakk/ili9341spi/SpiFlashReader.scala b/src/main/scala/ee/kivikakk/ili9341spi/SpiFlashReader.scala
@@ -6,7 +6,7 @@ import ee.hrzn.chryse.platform.Platform
 
 class SpiFlashReaderRequest extends Bundle {
   val addr = Output(UInt(24.W))
-  val len  = Output(UInt(16.W))
+  val len  = Output(UInt(32.W))
 }
 
 class SpiFlashReaderIO extends Bundle {
@@ -35,7 +35,7 @@ class SpiFlashReader(implicit platform: Platform) extends Module {
     0.U(unsignedBitLength(Seq(32, TRES1_TDP_CYCLES).max - 1).W),
   )
   val rcvBitRemReg  = RegInit(0.U(unsignedBitLength(7).W))
-  val rcvByteRemReg = RegInit(0.U(16.W))
+  val rcvByteRemReg = RegInit(0.U(32.W))
 
   val csReg = RegInit(false.B)
   pins.cs := csReg

diff --git a/src/main/scala/ee/kivikakk/ili9341spi/Top.scala b/src/main/scala/ee/kivikakk/ili9341spi/Top.scala
@@ -24,10 +24,7 @@ class IliIO extends Bundle {
 class Top(implicit platform: Platform) extends Module {
   override def desiredName = "ili9341spi"
 
-  val spiClock = RegInit(false.B)
-  spiClock := ~spiClock
-
-  val spifr = withClock(spiClock.asClock)(Module(new SpiFlashReader))
+  val spifr = Module(new SpiFlashReader)
   spifr.io.req.noenq()
   spifr.io.resp.nodeq()
 
@@ -50,7 +47,8 @@ class Top(implicit platform: Platform) extends Module {
   uart.io.tx :<>= lcd.io.resp
 
   object State extends ChiselEnum {
-    val sResetApply, sResetWait, sInitCmd, sInitParam, sWriteImg, sIdle = Value
+    val sResetApply, sResetWait, sInitCmd, sInitParam, sInitImg, sWriteImg,
+        sIdle = Value
   }
   val state         = RegInit(State.sResetApply)
   val resetApplyCyc = 11 * platform.clockHz / 1_000_000      // tRW_min = 10µs
@@ -61,7 +59,8 @@ class Top(implicit platform: Platform) extends Module {
   val initCmdRemReg = Reg(
     UInt(unsignedBitLength(LcdInit.sequence.map(_._2.length).max).W),
   )
-  val pngRomLen    = LcdInit.pngrom.length
+  val pngRomLen = LcdInit.pngrom.length
+  println(s"pngRomLen: $pngRomLen")
   val pngRomOffReg = Reg(UInt(unsignedBitLength(pngRomLen).W))
   // We spend quite a few cells on this. TODO (Chryse): BRAM init.
   // Cbf putting every tiny initted memory on SPI flash.
@@ -102,13 +101,8 @@ class Top(implicit platform: Platform) extends Module {
           }
         }
       }.otherwise {
-        state        := State.sWriteImg
+        state        := State.sInitImg
         pngRomOffReg := 0.U
-
-        val req = Wire(new SpiFlashReaderRequest)
-        req.addr := platform.asInstanceOf[PlatformFlashable].romFlashBase.U
-        req.len  := pngRomLen.U
-        spifr.io.req.enq(req)
       }
     }
     is(State.sInitParam) {
@@ -128,7 +122,26 @@ class Top(implicit platform: Platform) extends Module {
         state := State.sInitCmd
       }
     }
+    is(State.sInitImg) {
+      val req = Wire(new SpiFlashReaderRequest)
+      req.addr := platform.asInstanceOf[PlatformFlashable].romFlashBase.U
+      req.len  := pngRomLen.U
+      spifr.io.req.enq(req)
+
+      state := State.sWriteImg
+    }
     is(State.sWriteImg) {
+      val ehlo = uart.io.rx.deq()
+      when(uart.io.rx.fire && ehlo.byte === 1.U) {
+        uart.io.tx.enq(pngRomOffReg(7, 0))
+      }.elsewhen(uart.io.rx.fire && ehlo.byte === 2.U) {
+        uart.io.tx.enq(pngRomOffReg(15, 8))
+      }.elsewhen(uart.io.rx.fire && ehlo.byte === 3.U) {
+        uart.io.tx.enq(pngRomOffReg(17, 16))
+      }.elsewhen(uart.io.rx.fire && ehlo.byte === 4.U) {
+        uart.io.tx.enq(state.asUInt)
+      }
+
       when(pngRomOffReg =/= pngRomLen.U) {
         val resp = spifr.io.resp.deq()
         when(spifr.io.resp.fire) {

diff --git a/src/main/scala/ee/kivikakk/ili9341spi/lcd/LcdInit.scala b/src/main/scala/ee/kivikakk/ili9341spi/lcd/LcdInit.scala
@@ -37,7 +37,7 @@ object LcdInit {
       Seq(0x00.U, 0x0e.U, 0x14.U, 0x03.U, 0x11.U, 0x07.U, 0x31.U, 0xc1.U,
         0x48.U, 0x08.U, 0x0f.U, 0x0c.U, 0x31.U, 0x36.U, 0x0f.U),
     ),
-    (CASET, Seq(0x00.U, 0x00.U, 0x01.U, 0x30.U)),
+    (CASET, Seq(0x00.U, 0x00.U, 0x01.U, 0x3f.U)),
     (PASET, Seq(0x00.U, 0x00.U, 0x00.U, 0xef.U)),
     (SLEEP_OUT, Seq()),
     (NOP, Seq()), // stand-in that means "wait 120ms"