clean and cont.

build.sbt

@@ -1,4 +1,4 @@
-ThisBuild / scalaVersion         := "2.13.12"
+ThisBuild / scalaVersion         := "2.13.14"
 ThisBuild / version              := "0.1.0-SNAPSHOT"
 ThisBuild / versionScheme        := Some("early-semver")
 ThisBuild / homepage             := Some(url("https://github.com/kivikakk/ili9341spi"))

project/plugins.sbt

@@ -1 +1,3 @@
 logLevel := Level.Warn
+
+addSbtPlugin("org.scalameta" % "sbt-scalafmt" % "2.5.2")

src/main/scala/ee/kivikakk/ili9341spi/App.scala

@@ -4,10 +4,10 @@ import ee.hrzn.athena.flashable.PlatformFlashable
 import ee.hrzn.athena.flashable.SubcommandRom
 import ee.hrzn.chryse.ChryseApp
 import ee.hrzn.chryse.platform.Platform
-import ee.hrzn.chryse.platform.cxxrtl.CXXRTLOptions
-import ee.hrzn.chryse.platform.cxxrtl.CXXRTLPlatform
-import ee.hrzn.chryse.platform.ecp5.LFE5U_45F
-import ee.hrzn.chryse.platform.ecp5.ULX3SPlatform
+import ee.hrzn.chryse.platform.cxxrtl.CxxrtlOptions
+import ee.hrzn.chryse.platform.cxxrtl.CxxrtlPlatform
+import ee.hrzn.chryse.platform.ecp5.Lfe5U_45F
+import ee.hrzn.chryse.platform.ecp5.Ulx3SPlatform
 import ee.hrzn.chryse.platform.ice40.IceBreakerPlatform
 import ee.kivikakk.ili9341spi.lcd.LCDInit
 
@@ -21,7 +21,7 @@ object App extends ChryseApp {
         def romFlashCommand(binPath: String) =
           Seq("iceprog", "-o", f"0x$romFlashBase%x", binPath)
       },
-      new ULX3SPlatform(LFE5U_45F) with PlatformFlashable {
+      new Ulx3SPlatform(Lfe5U_45F) with PlatformFlashable {
         var romFlashBase = BigInt("00100000", 16)
         def romFlashCommand(binPath: String) =
           Seq(
@@ -38,8 +38,8 @@ object App extends ChryseApp {
     )
   override val additionalSubcommands = Seq(rom)
   override val cxxrtlOptions = Some(
-    CXXRTLOptions(
-      platforms = Seq(new CXXRTLPlatform("cxxrtl") { val clockHz = 3_000_000 }),
+    CxxrtlOptions(
+      platforms = Seq(new CxxrtlPlatform("cxxrtl") { val clockHz = 3_000_000 }),
     ),
   )
 

src/main/scala/ee/kivikakk/ili9341spi/SPIFlashReader.scala → src/main/scala/ee/kivikakk/ili9341spi/SpiFlashReader.scala

@@ -4,24 +4,26 @@ import chisel3._
 import chisel3.util._
 import ee.hrzn.chryse.platform.Platform
 
-class SPIFlashReaderIO extends Bundle {
-  val req = Flipped(Decoupled(new Bundle {
-    val addr = Output(UInt(24.W))
-    val len  = Output(UInt(16.W))
-  }))
+class SpiFlashReaderRequest extends Bundle {
+  val addr = Output(UInt(24.W))
+  val len  = Output(UInt(16.W))
+}
+
+class SpiFlashReaderIO extends Bundle {
+  val req  = Flipped(Decoupled(new SpiFlashReaderRequest))
   val resp = Decoupled(UInt(8.W))
 }
 
-class SPIPinsIO extends Bundle {
+class SpiPinsIO extends Bundle {
   val copi  = Output(Bool())
   val cipo  = Input(Bool())
   val cs    = Output(Bool())
   val clock = Output(Bool())
 }
 
-class SPIFlashReader(implicit platform: Platform) extends Module {
-  val io   = IO(new SPIFlashReaderIO)
-  val pins = IO(new SPIPinsIO)
+class SpiFlashReader(implicit platform: Platform) extends Module {
+  val io   = IO(new SpiFlashReaderIO)
+  val pins = IO(new SpiPinsIO)
 
   // tRES1 (/CS High to Standby Mode without ID Read) and tDP (/CS High to
   // Power-down Mode) are both max 3us.

src/main/scala/ee/kivikakk/ili9341spi/Top.scala

@@ -2,16 +2,17 @@ package ee.kivikakk.ili9341spi
 
 import chisel3._
 import chisel3.util._
-import ee.hrzn.athena.uart.UART
+import ee.hrzn.athena.flashable.PlatformFlashable
+import ee.hrzn.athena.uart.Uart
 import ee.hrzn.chryse.platform.Platform
-import ee.hrzn.chryse.platform.cxxrtl.CXXRTLPlatform
-import ee.hrzn.chryse.platform.ecp5.ULX3SPlatform
+import ee.hrzn.chryse.platform.cxxrtl.CxxrtlPlatform
+import ee.hrzn.chryse.platform.ecp5.Ulx3SPlatform
 import ee.hrzn.chryse.platform.ice40.IceBreakerPlatform
-import ee.kivikakk.ili9341spi.lcd.LCD
 import ee.kivikakk.ili9341spi.lcd.LCDInit
-import ee.kivikakk.ili9341spi.lcd.LCDRequest
+import ee.kivikakk.ili9341spi.lcd.LcdRequest
+import ee.kivikakk.ili9341spi.lcd.Lcd
 
-class ILIIO extends Bundle {
+class IliIO extends Bundle {
   val clk  = Output(Bool())
   val copi = Output(Bool())
   val res  = Output(Bool())
@@ -23,16 +24,19 @@ class ILIIO extends Bundle {
 class Top(implicit platform: Platform) extends Module {
   override def desiredName = "ili9341spi"
 
-  val spifr = Module(new SPIFlashReader)
+  val spiClock = RegInit(false.B)
+  spiClock := ~spiClock
+
+  val spifr = withClock(spiClock.asClock)(Module(new SpiFlashReader))
   spifr.io.req.noenq()
   spifr.io.resp.nodeq()
 
-  val ili    = Wire(new ILIIO)
+  val ili    = Wire(new IliIO)
   val resReg = RegInit(true.B) // start with reset on.
   ili.res := resReg
   ili.blk := true.B
 
-  val lcd = Module(new LCD)
+  val lcd = Module(new Lcd)
   ili.clk       := lcd.pins.clk
   ili.copi      := lcd.pins.copi
   ili.dc        := lcd.pins.dc
@@ -41,7 +45,7 @@ class Top(implicit platform: Platform) extends Module {
   lcd.io.req.noenq()
   lcd.io.resp.nodeq()
 
-  val uart = Module(new UART(baud = 115200))
+  val uart = Module(new Uart(baud = 115200))
   uart.io.rx.nodeq()
   uart.io.tx :<>= lcd.io.resp
 
@@ -80,7 +84,7 @@ class Top(implicit platform: Platform) extends Module {
     }
     is(State.sInitCmd) {
       when(initRomIxReg =/= initRomLen.U) {
-        val req = Wire(new LCDRequest())
+        val req = Wire(new LcdRequest())
         req.data    := initRom(initRomIxReg)
         req.dc      := true.B
         req.respLen := 0.U
@@ -100,11 +104,16 @@ class Top(implicit platform: Platform) extends Module {
       }.otherwise {
         state        := State.sWriteImg
         pngRomOffReg := 0.U
+
+        val req = Wire(new SpiFlashReaderRequest)
+        req.addr := platform.asInstanceOf[PlatformFlashable].romFlashBase.U
+        req.len  := pngRomLen.U
+        spifr.io.req.enq(req)
       }
     }
     is(State.sInitParam) {
       when(initCmdRemReg =/= 0.U) {
-        val req = Wire(new LCDRequest)
+        val req = Wire(new LcdRequest)
         req.data    := initRom(initRomIxReg)
         req.dc      := false.B
         req.respLen := 0.U
@@ -121,14 +130,14 @@ class Top(implicit platform: Platform) extends Module {
     }
     is(State.sWriteImg) {
       when(pngRomOffReg =/= pngRomLen.U) {
-        val req = Wire(new LCDRequest)
-        req.data := 0xff.U
-        // req.data    := pngRom(pngRomOffReg)
-        req.dc      := false.B
-        req.respLen := 0.U
-        lcd.io.req.enq(req)
+        val resp = spifr.io.resp.deq()
+        when(spifr.io.resp.fire) {
+          val req = Wire(new LcdRequest)
+          req.data    := resp
+          req.dc      := false.B
+          req.respLen := 0.U
+          lcd.io.req.enq(req)
 
-        when(lcd.io.req.fire) {
           pngRomOffReg := pngRomOffReg + 1.U
         }
       }.otherwise {
@@ -157,7 +166,7 @@ class Top(implicit platform: Platform) extends Module {
       plat.resources.spiFlash.wp    := false.B
       plat.resources.spiFlash.hold  := false.B
 
-    case plat: ULX3SPlatform =>
+    case plat: Ulx3SPlatform =>
       ili.cipo := false.B
 
       plat.resources.uart.tx := uart.pins.tx
@@ -170,8 +179,8 @@ class Top(implicit platform: Platform) extends Module {
       plat.resources.spiFlash.wp    := false.B
       plat.resources.spiFlash.hold  := false.B
 
-    case plat: CXXRTLPlatform =>
-      val io = IO(new ILIIO)
+    case plat: CxxrtlPlatform =>
+      val io = IO(new IliIO)
       io :<>= ili
 
       uart.pins.rx := false.B

src/main/scala/ee/kivikakk/ili9341spi/lcd/LCD.scala → src/main/scala/ee/kivikakk/ili9341spi/lcd/Lcd.scala

@@ -3,28 +3,28 @@ package ee.kivikakk.ili9341spi.lcd
 import chisel3._
 import chisel3.util._
 
-class LCDPinsIO extends Bundle {
+class LcdPinsIO extends Bundle {
   val clk  = Output(Bool())
   val copi = Output(Bool())
   val cipo = Input(Bool())
   val dc   = Output(Bool())
 }
 
-class LCDRequest extends Bundle {
+class LcdRequest extends Bundle {
   val data    = UInt(8.W)
   val dc      = Bool()
   val respLen = UInt(4.W)
 }
 
-class LCDIO extends Bundle {
-  val req  = Flipped(Decoupled(new LCDRequest))
+class LcdIO extends Bundle {
+  val req  = Flipped(Decoupled(new LcdRequest))
   val resp = Decoupled(UInt(8.W))
 }
 
-class LCD extends Module {
-  val io = IO(new LCDIO)
+class Lcd extends Module {
+  val io = IO(new LcdIO)
 
-  val pins = IO(new LCDPinsIO)
+  val pins = IO(new LcdPinsIO)
   pins.clk := false.B
 
   val dcReg = Reg(Bool())

src/main/scala/ee/kivikakk/ili9341spi/lcd/LCDInit.scala → src/main/scala/ee/kivikakk/ili9341spi/lcd/LcdInit.scala

@@ -21,7 +21,7 @@ object LCDInit {
     (POWER_CTRL_2, Seq(0x10.U)),
     (VCOM_CTRL_1, Seq(0x3e.U, 0x28.U)),
     (VCOM_CTRL_2, Seq(0x86.U)),
-    (MEMORY_ACCESS_CTRL, Seq(0x48.U)),
+    (MEMORY_ACCESS_CTRL, Seq(0x28.U)),
     (COLMOD, Seq(0x55.U)),
     (FRAME_RATE_CTRL, Seq(0x00.U, 0x18.U)),
     (DISPLAY_FN_CTRL, Seq(0x08.U, 0x82.U, 0x27.U)),
@@ -37,12 +37,12 @@ object LCDInit {
       Seq(0x00.U, 0x0e.U, 0x14.U, 0x03.U, 0x11.U, 0x07.U, 0x31.U, 0xc1.U,
         0x48.U, 0x08.U, 0x0f.U, 0x0c.U, 0x31.U, 0x36.U, 0x0f.U),
     ),
-    (CASET, Seq(0x00.U, 0x00.U, 0x00.U, 0x00.U)),
-    (PASET, Seq(0x00.U, 0x00.U, 0x00.U, 0x00.U)),
+    (CASET, Seq(0x00.U, 0x00.U, 0x01.U, 0x30.U)),
+    (PASET, Seq(0x00.U, 0x00.U, 0x00.U, 0xef.U)),
     (SLEEP_OUT, Seq()),
     (NOP, Seq()), // stand-in that means "wait 120ms"
     (DISPLAY_ON, Seq()),
-    (WRITE_MEMORY_CONTINUE, Seq()),
+    (MEMORY_WRITE, Seq()),
   )
 
   lazy val rom: Seq[UInt] = {

src/test/scala/ee/kivikakk/ili9341spi/lcd/SPISpec.scala → src/test/scala/ee/kivikakk/ili9341spi/lcd/LcdSpec.scala

@@ -4,12 +4,12 @@ import chisel3._
 import chisel3.simulator.EphemeralSimulator._
 import org.scalatest.flatspec.AnyFlatSpec
 
-class LCDSpec extends AnyFlatSpec {
-  behavior.of("LCD")
+class LcdSpec extends AnyFlatSpec {
+  behavior.of("Lcd")
 
   private val rand = new scala.util.Random
 
-  def snd(c: LCD, bytes: Seq[Byte], rcvCnt: Int = 0): Unit = {
+  def snd(c: Lcd, bytes: Seq[Byte], rcvCnt: Int = 0): Unit = {
     for { (byte, byteIx) <- bytes.zipWithIndex } {
       c.clock.step()
       c.pins.clk.expect(false.B, s"snd pins.clk @ $byteIx")
@@ -45,7 +45,7 @@ class LCDSpec extends AnyFlatSpec {
     c.io.req.ready.expect((rcvCnt == 0).B)
   }
 
-  def rcv(c: LCD, bytes: Seq[Byte]): Unit = {
+  def rcv(c: Lcd, bytes: Seq[Byte]): Unit = {
     for { (byte, byteIx) <- bytes.zipWithIndex } {
       for { bitIx <- 0 until 8 } {
         c.pins.clk.expect(false.B, s"rcv pins.clk @ $byteIx:$bitIx")
@@ -69,26 +69,26 @@ class LCDSpec extends AnyFlatSpec {
   }
 
   it should "transmit a 1-byte command packet" in {
-    simulate(new LCD) { c =>
+    simulate(new Lcd) { c =>
       snd(c, rand.nextBytes(1).toSeq)
     }
   }
 
   it should "transmit a 2-byte command packet" in {
-    simulate(new LCD) { c =>
+    simulate(new Lcd) { c =>
       snd(c, rand.nextBytes(2).toSeq)
     }
   }
 
   it should "read a 1-byte response to a command packet" in {
-    simulate(new LCD) { c =>
+    simulate(new Lcd) { c =>
       snd(c, rand.nextBytes(1).toSeq, 1)
       rcv(c, rand.nextBytes(1).toSeq)
     }
   }
 
   it should "read a 2-byte response to a command packet" in {
-    simulate(new LCD) { c =>
+    simulate(new Lcd) { c =>
       // TODO: optional cycle delay between send/receive. The datasheet is
       // ambiguous as to whether or not it should be just one cycle, or an
       // entire byte.