main_to_clock #4
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rloc_rc - wip - h_set probe,luts in chain on X with step 12 and Y8
wbj - uart - add u9 module from sch
wbj - uart - wip - ic_74htc193 add gates, syn ok
…k and we have something strange count wbj - uart - wip - ic_74htc193 fix warning
wbj - uart - ic_74htc193 fix ibuf
wbj - uart - ic_74htc193 implement tcu tcd output wbj - uart - ic_74htc193 add nand5 gate wbj - uart - add 74hct00 wbj - uart - ic_74htc193 disable ibuf
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