Toy RISC-V emulator
WARNING: If you are interested in testing your RISCV executables with an emulator, save yourself some time and use the official ones. This is a WIP and it's lacking A LOT of stuff. Also, the BIOS/Kernel isn't Linux-compatible, so it's probably not what you are looking for.
Ok, you are still here. My goal for this project is to build a basic RISC-V emulator (targeting RV32I only) which will in turn help me build a RISC-V circuit in DLS.
- Single cycle CPU with M and U mode support (ISA emulation)
- Simple BIOS/Kernel
- Virtual Hard Disk and a few small test apps
- Simple debugger
- Multi cycle CPU
- Caches
- Minimal pipelined CPU
- Branch prediction
- TODO: Add more goals here! :)
One important note: Performance isn't a concern for this project.
This project uses the following 3rd party libraries
MIT License
Copyright (c) 2017 Jim Drygiannakis
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