Adding VCD file import/export #33

steveschnepp · 2023-09-17T16:04:00Z

Only VCD export works, but the PR also contains some new features :

variable number of cycles per instructions. Traditional is 12T, but some are 2T and most current are 1T
enhance the history output when multicycle instructions are executed. This is important for more accurate VCD files
enhance the RESET. Can do proper Power cycles & IDLE.

It is a plaform setup task, there is little point in reloading it upon reset. Only the call is delegated to emu.c, the function itself is still in opcodes.c & disasm.c

Now able to emulate: * Warm RESET (only SFR) * Power-Cycle RESET (SFR + RAM) * Factory RESET (SFR + RAM + ROM)

The parameters added are - USE_SWITCH_DISPATCH=(0|1) - CYCLES_PER_INSTR=n - USE_LTO=(0|1)

* ssc/enhance-dispatch-strategy: Use ifdef for dispatch strategy Enhance the RESET capabilities Move the init to opcode/disasm calls to emu.c

This avoid showing a wrong opcode during multi-cycle instructions.

steveschnepp added 3 commits September 11, 2022 21:12

Move the init to opcode/disasm calls to emu.c

ee893fb

It is a plaform setup task, there is little point in reloading it upon reset. Only the call is delegated to emu.c, the function itself is still in opcodes.c & disasm.c

Enhance the RESET capabilities

c737238

Now able to emulate: * Warm RESET (only SFR) * Power-Cycle RESET (SFR + RAM) * Factory RESET (SFR + RAM + ROM)

Use ifdef for dispatch strategy

f2d378c

steveschnepp force-pushed the vcd branch from 3470d7c to 7da2773 Compare September 18, 2023 20:03

steveschnepp added 11 commits September 18, 2023 22:42

Add params to make

ae5c28a

The parameters added are - USE_SWITCH_DISPATCH=(0|1) - CYCLES_PER_INSTR=n - USE_LTO=(0|1)

Adding VCD file output

c6648d3

default optimize is -g

53285cd

support variable CYCLES_PER_INSTR

e0baefd

compile time cycles

2028304

refactor the IDLE & POWERDOWN handling

855207e

Merge remote-tracking branch 'ssc/enhance-dispatch-strategy' into vcd

4d565ef

* ssc/enhance-dispatch-strategy: Use ifdef for dispatch strategy Enhance the RESET capabilities Move the init to opcode/disasm calls to emu.c

using clocks per CPU

0d3e49b

enhancing some comments

350a3dd

explicit opcode to aid debugging

9d868fc

fix instruction steps

daa30a7

steveschnepp force-pushed the vcd branch 3 times, most recently from 4603c2a to 7aef7a2 Compare September 25, 2023 06:49

steveschnepp added 2 commits September 25, 2023 09:01

Delay PC update until the last instruction cycle.

f28fede

This avoid showing a wrong opcode during multi-cycle instructions.

Decode the instruction on their first cycle

74f7873

steveschnepp force-pushed the vcd branch from 7aef7a2 to 74f7873 Compare September 25, 2023 07:02

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Adding VCD file import/export #33

Adding VCD file import/export #33

steveschnepp commented Sep 17, 2023 •

edited

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Adding VCD file import/export #33

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steveschnepp commented Sep 17, 2023 • edited Loading

steveschnepp commented Sep 17, 2023 •

edited

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