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Use LLVMGPUTileandFuse instead of LLVMGPUVectorize for convolutions #19469

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merged 4 commits into from
Dec 13, 2024
+23 −12
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Use LLVMGPUTileandFuse instead of LLVMGPUVectorize for convolutions #19469

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155ce35
Use LLVMGPUTileandFuse instead of LLVMGPUVectorize for convolutions
nirvedhmeshram Dec 11, 2024
523fcdf
fix tests
nirvedhmeshram Dec 13, 2024
5286faa
better flag name
nirvedhmeshram Dec 13, 2024
479ce8f
fix flag description
nirvedhmeshram Dec 13, 2024
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26 changes: 19 additions & 7 deletions compiler/src/iree/compiler/Codegen/LLVMGPU/KernelConfig.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -77,6 +77,12 @@ llvm::cl::opt<bool> clGPUUnalignedGEMMVectorDistribution(
"unaligned GEMMs when supported"),
llvm::cl::init(false));

llvm::cl::opt<bool> clGPUUseTileAndFuseConvolution(
"iree-codegen-llvmgpu-use-tile-and-fuse-convolution",
llvm::cl::desc(
"test the tile and fuse pipeline for supported convolutions"),
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llvm::cl::init(true));

/// Flag to force using WMMA tensorcore operations.
llvm::cl::opt<bool>
clGPUUseWMMA("iree-codegen-llvmgpu-use-wmma",
Expand Down Expand Up @@ -2196,12 +2202,19 @@ static bool distributeToSquare(const int64_t oh, const int64_t ow,
// Convolution Pipeline Configuration
//====---------------------------------------------------------------------===//

static LogicalResult setConvolutionConfig(IREE::GPU::TargetAttr target,
linalg::LinalgOp linalgOp,
const int64_t bestTilingFactor) {
static LogicalResult setConvolutionConfig(
IREE::GPU::TargetAttr target, mlir::FunctionOpInterface entryPointFn,
linalg::LinalgOp linalgOp, const int64_t bestTilingFactor) {
if (!isa<linalg::Conv2DNhwcHwcfOp, linalg::Conv2DNchwFchwOp>(linalgOp)) {
return failure();
}
if (clGPUUseTileAndFuseConvolution) {
if (succeeded(IREE::GPU::setTileAndFuseLoweringConfig(target, entryPointFn,
linalgOp))) {
LDBG("Tile and fuse convolution config");
return success();
}
}
const bool isNCHW = isa<linalg::Conv2DNchwFchwOp>(*linalgOp);
const bool isNHWC = isa<linalg::Conv2DNhwcHwcfOp>(*linalgOp);

Expand Down Expand Up @@ -2284,9 +2297,8 @@ static LogicalResult setConvolutionConfig(IREE::GPU::TargetAttr target,
SmallVector<int64_t> windowTileSizes(4, 0);
windowTileSizes[ohIndex] = 1;
tileSizes.push_back(windowTileSizes);
auto funcOp = linalgOp->getParentOfType<mlir::FunctionOpInterface>();
return setOpConfigAndEntryPointFnTranslation(funcOp, linalgOp, tileSizes,
pipeline, workgroupSize);
return setOpConfigAndEntryPointFnTranslation(
entryPointFn, linalgOp, tileSizes, pipeline, workgroupSize);
}

//====---------------------------------------------------------------------===//
Expand Down Expand Up @@ -2340,7 +2352,7 @@ static LogicalResult setRootConfig(IREE::GPU::TargetAttr target,
LDBG("Warp Reduction Config");
return success();
}
if (succeeded(setConvolutionConfig(target, linalgOp, 16))) {
if (succeeded(setConvolutionConfig(target, entryPointFn, linalgOp, 16))) {
LDBG("Convolution Config");
return success();
}
Expand Down
2 changes: 1 addition & 1 deletion compiler/src/iree/compiler/Codegen/LLVMGPU/test/conv_pipeline_test_cuda.mlir
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@@ -1,4 +1,4 @@
// RUN: iree-opt --split-input-file --iree-gpu-test-target=sm_60 \
// RUN: iree-opt --split-input-file --iree-gpu-test-target=sm_60 --iree-codegen-llvmgpu-use-tile-and-fuse-convolution=false \
// RUN: --pass-pipeline='builtin.module(hal.executable(hal.executable.variant(builtin.module(iree-llvmgpu-select-lowering-strategy, func.func(iree-llvmgpu-lower-executable-target,canonicalize)))))' \
// RUN: %s | FileCheck %s

Expand Down
7 changes: 3 additions & 4 deletions compiler/src/iree/compiler/Codegen/LLVMGPU/test/gpu_set_num_workgroups.mlir
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Expand Up @@ -612,12 +612,11 @@ func.func @forward_dispatch_1_conv_2d_nhwc_hwcf_256x112x112x64x7x7x3_f32() {
return
}

// CHECK-DAG: #[[CONFIG:.+]] = #iree_codegen.lowering_config<tile_sizes = {{\[}}[1, 1, 8, 64, 1, 1, 4], [0, 1, 0, 0]{{\]}}
// CHECK-DAG: #[[TRANSLATION:.+]] = #iree_codegen.translation_info<pipeline = LLVMGPUVectorize workgroup_size = [16, 2, 1]>
// CHECK-DAG: #[[TRANSLATION:.+]] = #iree_codegen.translation_info<pipeline = LLVMGPUTileAndFuse workgroup_size = [32, 1, 1]
// CHECK: func.func @forward_dispatch_1_conv_2d_nhwc_hwcf_256x112x112x64x7x7x3_f32
// CHECK-SAME: translation_info = #[[TRANSLATION]]
// CHECK: linalg.generic
// CHECK-SAME: lowering_config = #[[CONFIG]]
// CHECK: linalg.conv_2d
// CHECK-SAME: lowering_config = #iree_gpu.lowering_config<{promote_operands = [0, 1], reduction = [0, 0, 0, 0, 1, 7, 3], thread = [1, 1, 1, 1, 0, 0, 0], workgroup = [1, 1, 1, 32, 0, 0, 0]}>

// -----

Expand Down
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