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[LLVMCPU] Enable tileDispatchUsingForall as default #18777

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merged 6 commits into from
Oct 25, 2024

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@pashu123 pashu123 force-pushed the cpudefault branch 2 times, most recently from f04f7e5 to b8eeba4 Compare October 22, 2024 03:51
Comment on lines +550 to +556
// TODO: Enable grouped convolution and depth wise pooling fusion.
// Rightnow, this is going through the default CPU pipeline and not through
// CONVTilingExpert.
if (isa<linalg::Conv2DNgchwFgchwOp, linalg::Conv2DNgchwGfchwOp,
linalg::PoolingNdhwcSumOp>(producer)) {
return false;
}
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Do we have an issue for this?

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These originate from some onnx models. I will file an issue.

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@ScottTodd This patch enables some of the tests in iree-test-suites. Shall I merge this and then update xfails from there?

pashu123 added a commit to pashu123/iree-test-suites that referenced this pull request Oct 24, 2024
These xfails start passing as a part of
iree-org/iree#18777 commit.
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@ScottTodd This patch enables some of the tests in iree-test-suites. Shall I merge this and then update xfails from there?

For onnx ops? I'm actually thinking about removing all the xfails for onnx ops in the iree-org/iree-test-suites repo, so we don't have tracking in two places: iree-org/iree-test-suites#35. This repo should definitely update the config file(s).

@pashu123 pashu123 merged commit 3b751a4 into iree-org:main Oct 25, 2024
35 of 36 checks passed
Eliasj42 pushed a commit that referenced this pull request Oct 31, 2024
pashu123 added a commit that referenced this pull request Nov 12, 2024
Add an additional level of tiling, aka vector parallel to the CPU
default pipeline. Some of the linalg op that is not specialized through
any pipeline may hit a bufferization issue if passed through the default
pipeline. Adding an extra level of tiling takes care of such cases.

Removes some ops (disabled for producer fusion) from dispatch Region
creation. They were added in #18777
. For more info: #18900
Groverkss pushed a commit to Groverkss/iree that referenced this pull request Dec 1, 2024
Add an additional level of tiling, aka vector parallel to the CPU
default pipeline. Some of the linalg op that is not specialized through
any pipeline may hit a bufferization issue if passed through the default
pipeline. Adding an extra level of tiling takes care of such cases.

Removes some ops (disabled for producer fusion) from dispatch Region
creation. They were added in iree-org#18777
. For more info: iree-org#18900
giacs-epic pushed a commit to giacs-epic/iree that referenced this pull request Dec 4, 2024
Add an additional level of tiling, aka vector parallel to the CPU
default pipeline. Some of the linalg op that is not specialized through
any pipeline may hit a bufferization issue if passed through the default
pipeline. Adding an extra level of tiling takes care of such cases.

Removes some ops (disabled for producer fusion) from dispatch Region
creation. They were added in iree-org#18777
. For more info: iree-org#18900

Signed-off-by: Giacomo Serafini <[email protected]>
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4 participants