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[VectorDistribution] Configure contraction layouts at linalg level
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157
compiler/src/iree/compiler/Codegen/LLVMGPU/LLVMGPUConfigureTensorLayouts.cpp
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| Original file line number | Diff line number | Diff line change |
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| // Copyright 2024 The IREE Authors | ||
| // | ||
| // Licensed under the Apache License v2.0 with LLVM Exceptions. | ||
| // See https://llvm.org/LICENSE.txt for license information. | ||
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception | ||
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| #include <algorithm> | ||
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| #include "iree/compiler/Codegen/Dialect/Codegen/IR/IREECodegenAttrs.h" | ||
| #include "iree/compiler/Codegen/Dialect/GPU/IR/IREEGPUAttrs.h" | ||
| #include "iree/compiler/Codegen/Dialect/VectorExt/IR/VectorExtDialect.h" | ||
| #include "iree/compiler/Codegen/LLVMGPU/PassDetail.h" | ||
| #include "iree/compiler/Codegen/LLVMGPU/Passes.h" | ||
| #include "iree/compiler/Codegen/Utils/GPUUtils.h" | ||
| #include "llvm/ADT/SetVector.h" | ||
| #include "llvm/Support/Debug.h" | ||
| #include "llvm/Support/MathExtras.h" | ||
| #include "llvm/Support/raw_ostream.h" | ||
| #include "mlir/Analysis/SliceAnalysis.h" | ||
| #include "mlir/Dialect/Vector/IR/VectorOps.h" | ||
| #include "mlir/IR/BuiltinAttributes.h" | ||
| #include "mlir/IR/BuiltinTypes.h" | ||
| #include "mlir/IR/PatternMatch.h" | ||
| #include "mlir/IR/TypeUtilities.h" | ||
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| #define DEBUG_TYPE "iree-llvmgpu-configure-vector-layouts" | ||
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| namespace mlir::iree_compiler { | ||
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| namespace { | ||
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| LogicalResult setContractionAnchor(IREE::GPU::MMAScheduleAttr schedule, | ||
| RewriterBase &rewriter, | ||
| linalg::GenericOp contract) { | ||
| // TODO: Add SIMT fallback. | ||
| if (!schedule) { | ||
| return contract->emitError("missing mma schedule for contraction"); | ||
| } | ||
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| // This function should have only be called on a contraction op. | ||
| assert(linalg::isaContractionOpInterface(contract) && | ||
| "cannot set contraction anchor on non contraction op"); | ||
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| auto layouts = schedule.getContractionLayout(contract); | ||
| if (failed(layouts)) { | ||
| return contract->emitError("cannot get concrete layout for contraction"); | ||
| } | ||
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| auto [aLayout, bLayout, cLayout] = *layouts; | ||
| Location loc = contract.getLoc(); | ||
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| Value lhs = contract.getOperand(0); | ||
| Value rhs = contract.getOperand(1); | ||
| Value acc = contract.getOperand(2); | ||
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| // Set layouts for lhs, rhs and acc. | ||
| rewriter.setInsertionPoint(contract); | ||
| auto layoutedLhs = rewriter.create<IREE::VectorExt::ToLayoutOp>( | ||
| loc, lhs.getType(), lhs, aLayout); | ||
| auto layoutedRhs = rewriter.create<IREE::VectorExt::ToLayoutOp>( | ||
| loc, rhs.getType(), rhs, bLayout); | ||
| auto layoutedAcc = rewriter.create<IREE::VectorExt::ToLayoutOp>( | ||
| loc, acc.getType(), acc, cLayout); | ||
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| // Promote matmul lhs and rhs. | ||
| // TODO: We should read this from the lowering_config on the operation. | ||
| // TODO: This is a hack until layout analysis is improved. The layout analysis | ||
| // should decide where to put these shared memory conversions. | ||
| layoutedLhs->setAttr("shared_memory_conversion", rewriter.getUnitAttr()); | ||
| layoutedRhs->setAttr("shared_memory_conversion", rewriter.getUnitAttr()); | ||
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| contract->setOperand(0, layoutedLhs.getResult()); | ||
| contract->setOperand(1, layoutedRhs.getResult()); | ||
| contract->setOperand(2, layoutedAcc.getResult()); | ||
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| // Set layout for result. | ||
| rewriter.setInsertionPointAfter(contract); | ||
| auto toLayout = rewriter.create<IREE::VectorExt::ToLayoutOp>( | ||
| loc, contract.getResult(0).getType(), contract.getResult(0), cLayout); | ||
| rewriter.replaceAllUsesExcept(contract.getResult(0), toLayout.getResult(), | ||
| toLayout); | ||
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| return success(); | ||
| } | ||
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| struct LLVMGPUConfigureTensorLayoutsPass | ||
| : public LLVMGPUConfigureTensorLayoutsBase< | ||
| LLVMGPUConfigureTensorLayoutsPass> { | ||
| public: | ||
| void getDependentDialects(DialectRegistry ®istry) const override { | ||
| registry.insert<IREE::VectorExt::IREEVectorExtDialect>(); | ||
| registry.insert<vector::VectorDialect>(); | ||
| } | ||
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| void runOnOperation() override { | ||
| auto func = getOperation(); | ||
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| std::array<int64_t, 3> workgroupSize; | ||
| if (func->hasAttr("workgroup_size")) { | ||
| auto tmpSizes = | ||
| llvm::cast<ArrayAttr>(func->getAttr("workgroup_size")).getValue(); | ||
| for (auto [i, size] : llvm::enumerate(tmpSizes)) { | ||
| workgroupSize[i] = llvm::cast<IntegerAttr>(size).getInt(); | ||
| } | ||
| } else { | ||
| std::optional<SmallVector<int64_t>> maybeWorkgroupSize = | ||
| getWorkgroupSize(func); | ||
| if (!maybeWorkgroupSize) { | ||
| func->emitOpError() | ||
| << "unable to query workgroup_size information from entry point"; | ||
| return signalPassFailure(); | ||
| } | ||
| for (auto [index, value] : llvm::enumerate(maybeWorkgroupSize.value())) { | ||
| workgroupSize[index] = value; | ||
| } | ||
| for (auto index : llvm::seq<size_t>(maybeWorkgroupSize->size(), 3)) { | ||
| workgroupSize[index] = 1; | ||
| } | ||
| } | ||
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| llvm::StringLiteral scheduleAttrName = | ||
| IREE::GPU::MMAScheduleAttr::getMnemonic(); | ||
| auto scheduleAttr = | ||
| func->getAttrOfType<IREE::GPU::MMAScheduleAttr>(scheduleAttrName); | ||
| if (!scheduleAttr) { | ||
| DictionaryAttr configDict = getTranslationInfo(func).getConfiguration(); | ||
| scheduleAttr = dyn_cast_or_null<IREE::GPU::MMAScheduleAttr>( | ||
| configDict.get(scheduleAttrName)); | ||
| } | ||
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| // Vector layout option setter aimed at contractions. For now, layout | ||
| // setting for other problems like reductions is TODO. | ||
| SmallVector<linalg::GenericOp> contracts; | ||
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| func->walk([&](linalg::GenericOp linalgOp) { | ||
| if (linalg::isaContractionOpInterface(linalgOp)) { | ||
| contracts.push_back(linalgOp); | ||
| } | ||
| }); | ||
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| IRRewriter rewriter(func); | ||
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| for (linalg::GenericOp contract : contracts) { | ||
| if (failed(setContractionAnchor(scheduleAttr, rewriter, contract))) { | ||
| return signalPassFailure(); | ||
| } | ||
| } | ||
| } | ||
| }; | ||
| } // namespace | ||
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| std::unique_ptr<InterfacePass<mlir::FunctionOpInterface>> | ||
| createLLVMGPUConfigureTensorLayouts() { | ||
| return std::make_unique<LLVMGPUConfigureTensorLayoutsPass>(); | ||
| } | ||
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| } // namespace mlir::iree_compiler |
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