Address multiple comments

Signed-off-by: erman-gurses <[email protected]>
iree-org · Oct 29, 2024 · 595f8ec · 595f8ec
1 parent 5295314
commit 595f8ec
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diff --git a/linalg_ops/convolution/CMakeLists.txt b/linalg_ops/convolution/CMakeLists.txt
@@ -12,26 +12,30 @@ list(APPEND _SIZES "large")
 list(APPEND _SIZES "medium")
 list(APPEND _SIZES "small")
 
+
+set(_DTYPES_AND_LAYOUTS)
+list(APPEND _DTYPES_AND_LAYOUTS "f16_nhwc_f16_hwcf_f16")
+list(APPEND _DTYPES_AND_LAYOUTS "f16_nchw_f16_fchw_f16")
+list(APPEND _DTYPES_AND_LAYOUTS "f16_nhwc_f16_hwcf_f32")
+list(APPEND _DTYPES_AND_LAYOUTS "f16_nchw_f16_fchw_f32")
+list(APPEND _DTYPES_AND_LAYOUTS "f32_nhwc_f32_hwcf_f32")
+list(APPEND _DTYPES_AND_LAYOUTS "f32_nchw_f32_fchw_f32")
+
 ###############################################################################
 #
 # CPU - llvm-cpu on local-task, default flags.
 #
 ###############################################################################
 
-
-set(_DTYPES)
-list(APPEND _DTYPES "f16_f16_f16")
-list(APPEND _DTYPES "f32_f32_f32")
-
-foreach(_DTYPE IN LISTS _DTYPES)
+foreach(_DTYPE_AND_LAYOUT IN LISTS _DTYPES_AND_LAYOUTS)
   foreach(_SIZE IN LISTS _SIZES)
     iree_test_suites_runner_test(
       NAME
-        conv2d_${_DTYPE}_${_SIZE}
+        conv2d_llvm-cpu_local-task_${_DTYPE_AND_LAYOUT}_${_SIZE}
       TESTS_SRC
-        "generated/${_DTYPE}/conv2d_${_DTYPE}_${_SIZE}.mlir"
+        "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}.mlir"
       CALLS_SRC
-        "generated/${_DTYPE}/conv2d_${_DTYPE}_${_SIZE}_calls.mlir"
+        "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}_calls.mlir"
       TEST_RUNNER
         iree-test-suites_iree-e2e-conv2d-test
       TARGET_BACKEND
@@ -47,15 +51,21 @@ foreach(_DTYPE IN LISTS _DTYPES)
   endforeach()
 endforeach()
 
-foreach(_DTYPE IN LISTS _DTYPES)
+###############################################################################
+#
+# CPU - Winograd llvm-cpu on local-task, default flags.
+#
+###############################################################################
+
+foreach(_DTYPE_AND_LAYOUT IN LISTS _DTYPES_AND_LAYOUTS)
   foreach(_SIZE IN LISTS _SIZES)
     iree_test_suites_runner_test(
       NAME
-        conv2d_winograd_${_DTYPE}_${_SIZE}
+        conv2d_winograd_llvm-cpu_local-task_${_DTYPE_AND_LAYOUT}_${_SIZE}
       TESTS_SRC
-        "generated/${_DTYPE}/conv2d_${_DTYPE}_${_SIZE}.mlir"
+        "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}.mlir"
       CALLS_SRC
-        "generated/${_DTYPE}/conv2d_${_DTYPE}_${_SIZE}_calls.mlir"
+        "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}_calls.mlir"
       TEST_RUNNER
         iree-test-suites_iree-e2e-conv2d-test
       TARGET_BACKEND
@@ -76,24 +86,47 @@ endforeach()
 
 ###############################################################################
 #
-# GPU - ROCm/HIP, default flags.
+# GPU - ROCm/HIP, CDNA(gfx9).
 #
 ###############################################################################
 
 # To distinguish between CDNA(gfx9) and RDNA3(gfx11)
 if(IREE_HIP_TEST_TARGET_CHIP MATCHES "^gfx9")
 
-set(_DTYPES_AND_LAYOUTS)
-list(APPEND _DTYPES_AND_LAYOUTS "f16_nhwc_f16_hwcf_f32")
-list(APPEND _DTYPES_AND_LAYOUTS "f16_nchw_f16_fchw_f32")
-list(APPEND _DTYPES_AND_LAYOUTS "i8_nhwc_i8_hwcf_i32")
+foreach(_DTYPE_AND_LAYOUT IN LISTS _DTYPES_AND_LAYOUTS)
+  foreach(_SIZE IN LISTS _SIZES)
+    iree_test_suites_runner_test(
+      NAME
+        conv2d_rocm_hip_${_DTYPE_AND_LAYOUT}_${_SIZE}
+      TESTS_SRC
+        "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}.mlir"
+      CALLS_SRC
+        "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}_calls.mlir"
+      TEST_RUNNER
+        iree-test-suites_iree-e2e-conv2d-test
+      TARGET_BACKEND
+        "rocm"
+      DRIVER
+        "hip"
+      COMPILER_FLAGS
+        "--iree-hip-target=${IREE_HIP_TEST_TARGET_CHIP}"
+      RUNNER_FLAGS
+      LABELS
+    )
+  endforeach()
+endforeach()
 
+###############################################################################
+#
+# Winograd GPU - ROCm/HIP, CDNA(gfx9).
+#
+###############################################################################
 
 foreach(_DTYPE_AND_LAYOUT IN LISTS _DTYPES_AND_LAYOUTS)
   foreach(_SIZE IN LISTS _SIZES)
     iree_test_suites_runner_test(
       NAME
-        conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}
+        conv2d_winograd_rocm_hip_${_DTYPE_AND_LAYOUT}_${_SIZE}
       TESTS_SRC
         "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}.mlir"
       CALLS_SRC
@@ -105,23 +138,156 @@ foreach(_DTYPE_AND_LAYOUT IN LISTS _DTYPES_AND_LAYOUTS)
       DRIVER
         "hip"
       COMPILER_FLAGS
+        "--iree-preprocessing-pass-pipeline=builtin.module\(func.func\(iree-linalg-ext-convert-conv2d-to-winograd{replace-all-convs=true}\)\)"
         "--iree-hip-target=${IREE_HIP_TEST_TARGET_CHIP}"
       RUNNER_FLAGS
       LABELS
     )
   endforeach()
 endforeach()
 
+###############################################################################
+#
+# GPU - ROCm/HIP, CDNA(gfx11)
+#
+###############################################################################
+
 elseif(IREE_HIP_TEST_TARGET_CHIP MATCHES "^gfx11")
 
+foreach(_DTYPE_AND_LAYOUT IN LISTS _DTYPES_AND_LAYOUTS)
+  foreach(_SIZE IN LISTS _SIZES)
+    iree_test_suites_runner_test(
+      NAME
+        conv2d_rocm_hip_${_DTYPE_AND_LAYOUT}_${_SIZE}
+      TESTS_SRC
+        "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}.mlir"
+      CALLS_SRC
+        "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}_calls.mlir"
+      TEST_RUNNER
+        iree-test-suites_iree-e2e-conv2d-test
+      TARGET_BACKEND
+        "rocm"
+      DRIVER
+        "hip"
+      COMPILER_FLAGS
+        "--iree-hip-target=${IREE_HIP_TEST_TARGET_CHIP}"
+      RUNNER_FLAGS
+      LABELS
+    )
+  endforeach()
+endforeach()
+
+###############################################################################
+#
+# Winograd GPU - ROCm/HIP, CDNA(gfx11).
+#
+###############################################################################
+
+foreach(_DTYPE_AND_LAYOUT IN LISTS _DTYPES_AND_LAYOUTS)
+  foreach(_SIZE IN LISTS _SIZES)
+    iree_test_suites_runner_test(
+      NAME
+        conv2d_winograd_rocm_hip_${_DTYPE_AND_LAYOUT}_${_SIZE}
+      TESTS_SRC
+        "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}.mlir"
+      CALLS_SRC
+        "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}_calls.mlir"
+      TEST_RUNNER
+        iree-test-suites_iree-e2e-conv2d-test
+      TARGET_BACKEND
+        "rocm"
+      DRIVER
+        "hip"
+      COMPILER_FLAGS
+        "--iree-preprocessing-pass-pipeline=builtin.module\(func.func\(iree-linalg-ext-convert-conv2d-to-winograd{replace-all-convs=true}\)\)"
+        "--iree-hip-target=${IREE_HIP_TEST_TARGET_CHIP}"
+      RUNNER_FLAGS
+      LABELS
+    )
+  endforeach()
+endforeach()
+
+endif()
+
+# CPU and GPU tests for "i8_nhwc_i8_hwcf_i32" combination without Winograd
 set(_DTYPES_AND_LAYOUTS)
-list(APPEND _DTYPES_AND_LAYOUTS "f16_nhwc_f16_hwcf_f32")
+list(APPEND _DTYPES_AND_LAYOUTS "i8_nhwc_i8_hwcf_i32")
+list(APPEND _DTYPES_AND_LAYOUTS "i8_nchw_i8_fchw_i32")
+
+###############################################################################
+#
+# CPU - llvm-cpu on local-task, default flags.
+#
+###############################################################################
+
+foreach(_DTYPE_AND_LAYOUT IN LISTS _DTYPES_AND_LAYOUTS)
+  foreach(_SIZE IN LISTS _SIZES)
+    iree_test_suites_runner_test(
+      NAME
+        conv2d_llvm-cpu_local-task_${_DTYPE_AND_LAYOUT}_${_SIZE}
+      TESTS_SRC
+        "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}.mlir"
+      CALLS_SRC
+        "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}_calls.mlir"
+      TEST_RUNNER
+        iree-test-suites_iree-e2e-conv2d-test
+      TARGET_BACKEND
+        "llvm-cpu"
+      DRIVER
+        "local-task"
+      COMPILER_FLAGS
+      RUNNER_FLAGS
+      LABELS
+         "hostonly"
+         "local"
+    )
+  endforeach()
+endforeach()
+
+###############################################################################
+#
+# GPU - ROCm/HIP, CDNA(gfx9).
+#
+###############################################################################
+
+# To distinguish between CDNA(gfx9) and RDNA3(gfx11)
+if(IREE_HIP_TEST_TARGET_CHIP MATCHES "^gfx9")
+
+foreach(_DTYPE_AND_LAYOUT IN LISTS _DTYPES_AND_LAYOUTS)
+  foreach(_SIZE IN LISTS _SIZES)
+    iree_test_suites_runner_test(
+      NAME
+        conv2d_rocm_hip_${_DTYPE_AND_LAYOUT}_${_SIZE}
+      TESTS_SRC
+        "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}.mlir"
+      CALLS_SRC
+        "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}_calls.mlir"
+      TEST_RUNNER
+        iree-test-suites_iree-e2e-conv2d-test
+      TARGET_BACKEND
+        "rocm"
+      DRIVER
+        "hip"
+      COMPILER_FLAGS
+        "--iree-hip-target=${IREE_HIP_TEST_TARGET_CHIP}"
+      RUNNER_FLAGS
+      LABELS
+    )
+  endforeach()
+endforeach()
+
+###############################################################################
+#
+# GPU - ROCm/HIP, CDNA(gfx11)
+#
+###############################################################################
+elseif(IREE_HIP_TEST_TARGET_CHIP MATCHES "^gfx11")
 
 foreach(_DTYPE_AND_LAYOUT IN LISTS _DTYPES_AND_LAYOUTS)
   foreach(_SIZE IN LISTS _SIZES)
     iree_test_suites_runner_test(
       NAME
-        conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}
+        conv2d_rocm_hip_${_DTYPE_AND_LAYOUT}_${_SIZE}
       TESTS_SRC
         "generated/${_DTYPE_AND_LAYOUT}/conv2d_${_DTYPE_AND_LAYOUT}_${_SIZE}.mlir"
       CALLS_SRC

diff --git a/linalg_ops/convolution/generate_e2e_conv2d_tests.py b/linalg_ops/convolution/generate_e2e_conv2d_tests.py
@@ -120,7 +120,7 @@ def get_test_shapes(shapes_id: ShapesId):
         return [
             TestShape(n=2, c=2, h=32, w=32, kh=3, kw=3, f=2, accumulate=True),
             TestShape(n=2, c=2, h=32, w=32, kh=3, kw=3, f=64, accumulate=True),
-            TestShape(n=2, c=32, h=32, w=32, kh=3, kw=3, f=64, accumulate=True),
+            TestShape(n=2, c=16, h=32, w=32, kh=3, kw=3, f=64, accumulate=True),
         ]
     if shapes_id == ShapesId.LARGE:
         return [

diff --git a/linalg_ops/convolution/generate_test_mlir_files.sh b/linalg_ops/convolution/generate_test_mlir_files.sh
@@ -13,20 +13,20 @@
 #   linalg_ops/
 #     convolution/
 #       generated/
-#         f16_f16_f16/
-#           conv2d_f16_f16_f16_large_calls.mlir
-#           conv2d_f16_f16_f16_large.mlir
-#           conv2d_f16_f16_f16_medium_calls.mlir
-#           conv2d_f16_f16_f16_medium.mlir
-#           conv2d_f16_f16_f16_small_calls.mlir
-#           conv2d_f16_f16_f16_small.mlir
-#         f32_f32_f32/
-#           conv2d_f32_f32_f32_large_calls.mlir
-#           conv2d_f32_f32_f32_large.mlir
-#           conv2d_f32_f32_f32_medium_calls.mlir
-#           conv2d_f32_f32_f32_medium.mlir
-#           conv2d_f32_f32_f32_small_calls.mlir
-#           conv2d_f32_f32_f32_small.mlir
+#         f16_nchw_f16_fchw_f16/
+#           conv2d_f16_nchw_f16_fchw_f16_large_calls.mlir
+#           conv2d_f16_nchw_f16_fchw_f16_large.mlir
+#           conv2d_f16_nchw_f16_fchw_f16_medium_calls.mlir
+#           conv2d_f16_nchw_f16_fchw_f16_medium.mlir
+#           conv2d_f16_nchw_f16_fchw_f16_small_calls.mlir
+#           conv2d_f16_nchw_f16_fchw_f16_small.mlir
+#         f16_nchw_f16_fchw_f32/
+#           conv2d_f16_nchw_f16_fchw_f32_large_calls.mlir
+#           conv2d_f16_nchw_f16_fchw_f32_large.mlir
+#           conv2d_f16_nchw_f16_fchw_f32_medium_calls.mlir
+#           conv2d_f16_nchw_f16_fchw_f32_medium.mlir
+#           conv2d_f16_nchw_f16_fchw_f32_small_calls.mlir
+#           conv2d_f16_nchw_f16_fchw_f32_small.mlir
 #         ...
 #           ...
 # Usage:
@@ -47,52 +47,30 @@ shapes=(
   "large"
 )
 
-# input_type;kernel_type;acc_type
-type_combinations=(
-  "f16;f16;f16"
-  "f32;f32;f32"
-)
-
-for type_combination in ${type_combinations[@]}; do
-  IFS=";" read -r -a types <<< "${type_combination}"
-  input_type="${types[0]}"
-  kernel_type="${types[1]}"
-  acc_type="${types[2]}"
-
-  type_name="${input_type}_${kernel_type}_${acc_type}"
-  type_combination_dir="${generated_dir_root}/${type_name}"
-  mkdir -p ${type_combination_dir}
-
-  for shape in ${shapes[@]}; do
-    echo "Generating conv2d test files for ${type_name}_${shape}"
-
-    name="conv2d_${type_name}_${shape}"
-    python ${this_dir}/generate_e2e_conv2d_tests.py \
-      --output_conv2d_mlir=${type_combination_dir}/${name}.mlir \
-      --output_calls_mlir=${type_combination_dir}/${name}_calls.mlir \
-      --input_type=${input_type} \
-      --kernel_type=${kernel_type} \
-      --acc_type=${acc_type} \
-      --shapes=${shape}
-  done
-done
-
 # input_type;input_layout;kernel_type;kernel_layout;acc_type
 type_and_layout_combinations=(
+  "f16;nhwc;f16;hwcf;f16"
+  "f16;nchw;f16;fchw;f16"
   "f16;nhwc;f16;hwcf;f32"
   "f16;nchw;f16;fchw;f32"
+  "f32;nhwc;f32;hwcf;f32"
+  "f32;nchw;f32;fchw;f32"
   "i8;nhwc;i8;hwcf;i32"
+  "i8;nchw;i8;fchw;i32"
 )
+
 for type_and_layout_combination in ${type_and_layout_combinations[@]}; do
   IFS=";" read -r -a combination <<< "${type_and_layout_combination}"
   input_type="${combination[0]}"
   input_layout="${combination[1]}"
   kernel_type="${combination[2]}"
   kernel_layout="${combination[3]}"
   acc_type="${combination[4]}"
+
   type_layout_name="${input_type}_${input_layout}_${kernel_type}_${kernel_layout}_${acc_type}"
   type_combination_dir="${generated_dir_root}/${type_layout_name}"
   mkdir -p ${type_combination_dir}
+
   for shape in ${shapes[@]}; do
     echo "Generating conv2d test files for ${type_layout_name}_${shape}"
     name="conv2d_${type_layout_name}_${shape}"

diff --git a/...f16_f16_f16/conv2d_f16_f16_f16_large.mlir → ...6/conv2d_f16_nchw_f16_fchw_f16_large.mlir b/...f16_f16_f16/conv2d_f16_f16_f16_large.mlir → ...6/conv2d_f16_nchw_f16_fchw_f16_large.mlir
diff --git a/...6_f16/conv2d_f16_f16_f16_large_calls.mlir → ...2d_f16_nchw_f16_fchw_f16_large_calls.mlir b/...6_f16/conv2d_f16_f16_f16_large_calls.mlir → ...2d_f16_nchw_f16_fchw_f16_large_calls.mlir
diff --git a/...16_f16_f16/conv2d_f16_f16_f16_medium.mlir → .../conv2d_f16_nchw_f16_fchw_f16_medium.mlir b/...16_f16_f16/conv2d_f16_f16_f16_medium.mlir → .../conv2d_f16_nchw_f16_fchw_f16_medium.mlir
@@ -6,7 +6,7 @@ func.func @conv2d_accumulate_2_2_32_32_times_3_3_64_dtype_f16_f16_f16(%lhs: tens
   %result = linalg.conv_2d_nchw_fchw {dilations = dense<[1, 1]> : tensor<2xi64>, strides = dense<[1, 1]> : tensor<2xi64>} ins(%lhs, %rhs: tensor<2x2x32x32xf16>, tensor<64x2x3x3xf16>) outs(%acc: tensor<2x64x30x30xf16>) -> tensor<2x64x30x30xf16>
   return %result: tensor<2x64x30x30xf16>
 }
-func.func @conv2d_accumulate_2_32_32_32_times_3_3_64_dtype_f16_f16_f16(%lhs: tensor<2x32x32x32xf16>, %rhs: tensor<64x32x3x3xf16>, %acc: tensor<2x64x30x30xf16>) -> tensor<2x64x30x30xf16> {
-  %result = linalg.conv_2d_nchw_fchw {dilations = dense<[1, 1]> : tensor<2xi64>, strides = dense<[1, 1]> : tensor<2xi64>} ins(%lhs, %rhs: tensor<2x32x32x32xf16>, tensor<64x32x3x3xf16>) outs(%acc: tensor<2x64x30x30xf16>) -> tensor<2x64x30x30xf16>
+func.func @conv2d_accumulate_2_16_32_32_times_3_3_64_dtype_f16_f16_f16(%lhs: tensor<2x16x32x32xf16>, %rhs: tensor<64x16x3x3xf16>, %acc: tensor<2x64x30x30xf16>) -> tensor<2x64x30x30xf16> {
+  %result = linalg.conv_2d_nchw_fchw {dilations = dense<[1, 1]> : tensor<2xi64>, strides = dense<[1, 1]> : tensor<2xi64>} ins(%lhs, %rhs: tensor<2x16x32x32xf16>, tensor<64x16x3x3xf16>) outs(%acc: tensor<2x64x30x30xf16>) -> tensor<2x64x30x30xf16>
   return %result: tensor<2x64x30x30xf16>
 }