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[SYCL] Support for load/store cache controls #11584
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f19cdb3
[SYCL] Proposed cache control properties for annotated_ptr.
rdeodhar e80276e
Updated doc based on review comments.
rdeodhar 81d91c7
Cleanup of doc.
rdeodhar 8725dfc
Formatting changes.
rdeodhar b994128
[SYCL] Support for cache control properties on annotated_ptr.
rdeodhar 21a78ec
Merge branch 'sycl' of https://github.com/intel/llvm into cachectrl
rdeodhar e097acb
Formatting change.
rdeodhar b21d9c2
Merge branch 'sycl' of https://github.com/intel/llvm into cachectrl
rdeodhar f847ea3
Change in syntax.
rdeodhar c0eab2c
Merge branch 'sycl' of https://github.com/intel/llvm into cachectrl
rdeodhar 0a54f88
Added missing #include.
rdeodhar 5d19fae
Added checks for cache_modes used in read and write hints.
rdeodhar 806ff86
Merge branch 'sycl' of https://github.com/intel/llvm into cachectrl
rdeodhar b8df87e
Minor corrections to namespace usage.
rdeodhar 482f9be
Update to documentation.
rdeodhar dc9b4ef
Renamed some read_hints as read_assertions.
rdeodhar 7fd8d7f
Merge branch 'sycl' of https://github.com/intel/llvm into cachectrl
rdeodhar bf9fba6
Changed structure of document describing cache controls and added a t…
rdeodhar be39b74
Formatting change.
rdeodhar a017630
Removed annotated_arg changes.
rdeodhar 8a1999e
Merge branch 'sycl' of https://github.com/intel/llvm into cachectrl
rdeodhar ac6597c
Formatting change.
rdeodhar f638d43
Restore damaged file.
rdeodhar 6fafa9c
Corrected cut-paste erros in doc.
rdeodhar 3c5720c
General cleanup and enhanced a test.
rdeodhar ac3bcdc
Merge branch 'sycl' of https://github.com/intel/llvm into cachectrl
rdeodhar d745c62
Formatting change.
rdeodhar ea7e677
Test update.
rdeodhar 5ef494d
Fixed merge error.
rdeodhar fc87598
Removed some unused declarations.
rdeodhar abf4bcf
Update sycl/doc/extensions/proposed/sycl_ext_intel_cache_controls.asc…
rdeodhar b9ae23c
Update sycl/doc/extensions/proposed/sycl_ext_intel_cache_controls.asc…
rdeodhar 904190a
Update sycl/doc/extensions/proposed/sycl_ext_intel_cache_controls.asc…
rdeodhar 34f9bc6
Merge branch 'sycl' of https://github.com/intel/llvm into cachectrl
rdeodhar 6981032
Merge branch 'cachectrl' of https://github.com/rdeodhar/llvm into cac…
rdeodhar 11e7887
Update sycl/doc/extensions/proposed/sycl_ext_intel_cache_controls.asc…
rdeodhar d44e645
Merge branch 'cachectrl' of https://github.com/rdeodhar/llvm into cac…
rdeodhar 694676b
Added comments noting need for consistency in cache_mode definition.
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Is there a design document or specifications for LLVM/SPIR-V levels?
Cache controls are using annotated pointer design. Right?
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The SPIR-V extension is here: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_cache_controls.asciidoc
This implementation builds upon annotated_ptr by adding new properties.
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Thanks. I also find KhronosGroup/SPIRV-LLVM-Translator#2140, which documents the LLVM IR representation of cache controls.