Load all host MSRs manually

Restore manually loading below MSRs. This is because automatic loading these MSRs conflicts with the SGX feature and then BSOD occurs on host rebooting. * IA32_PMC0 .. IA32_PMC3 * IA32_PERFEVTSEL0 .. IA32_PERFEVTSEL3 Signed-off-by: Wenchao Wang <[email protected]>
intel · Oct 10, 2022 · afdc568 · afdc568
1 parent c94d1ae
commit afdc568
Show file tree

Hide file tree

Showing 2 changed files with 8 additions and 24 deletions.
diff --git a/core/include/cpu.h b/core/include/cpu.h
@@ -45,12 +45,6 @@ struct vcpu_t;
 struct vcpu_state_t;
 
 #define NR_HMSR 6
-// The number of MSRs to be loaded on VM exits
-// Currently the MSRs list only supports automatic loading of below MSRs, the
-// total count of which is 8.
-// * IA32_PMCx
-// * IA32_PERFEVTSELx
-#define NR_HMSR_AUTOLOAD 8
 
 struct hstate {
     /* ldt is not covered by host vmcs area */
@@ -71,7 +65,6 @@ struct hstate {
     uint64_t fs_base;
     uint64_t hcr2;
     struct vmx_msr hmsr[NR_HMSR];
-    vmx_msr_entry hmsr_autoload[NR_HMSR_AUTOLOAD];
     // IA32_PMCx, since APM v1
     uint64_t apm_pmc_msrs[APM_MAX_GENERAL_COUNT];
     // IA32_PERFEVTSELx, since APM v1

diff --git a/core/vcpu.c b/core/vcpu.c
@@ -1045,7 +1045,6 @@ static void load_host_msr(struct vcpu_t *vcpu)
     int i;
     struct hstate *hstate = &get_cpu_data(vcpu->cpu_id)->hstate;
     bool em64t_support = cpu_has_feature(X86_FEATURE_EM64T);
-    uint32_t count = 0;
 
     // Load below MSR values manually on VM exits.
 
@@ -1072,23 +1071,16 @@ static void load_host_msr(struct vcpu_t *vcpu)
     if (!hax->apm_version)
         return;
 
-    // Load below MSR values automatically on VM exits.
-
-    // TODO: It will be implemented to trap IA32_PERFEVTSELx MSRs and
-    // automatically load below host values only when IA32_PERFEVTSELx MSRs are
-    // changed during the guest runtime.
+    // * IA32_PMCx and IA32_PERFEVTSELx
+    //   BSOD will occur in the host with SGX enabled when rebooting host on
+    //   automatic load.
     // APM v1: restore IA32_PMCx and IA32_PERFEVTSELx
     for (i = 0; i < (int)hax->apm_general_count; ++i) {
-        hstate->hmsr_autoload[count].index = (uint32_t)(IA32_PMC0 + i);
-        hstate->hmsr_autoload[count++].data = hstate->apm_pmc_msrs[i];
-    }
-
-    for (i = 0; i < (int)hax->apm_general_count; ++i) {
-        hstate->hmsr_autoload[count].index = (uint32_t)(IA32_PERFEVTSEL0 + i);
-        hstate->hmsr_autoload[count++].data = hstate->apm_pes_msrs[i];
+        uint32_t msr = (uint32_t)(IA32_PMC0 + i);
+        ia32_wrmsr(msr, hstate->apm_pmc_msrs[i]);
+        msr = (uint32_t)(IA32_PERFEVTSEL0 + i);
+        ia32_wrmsr(msr, hstate->apm_pes_msrs[i]);
     }
-
-    vmwrite(vcpu, VMX_EXIT_MSR_LOAD_COUNT, count);
 }
 
 static inline bool is_host_debug_enabled(struct vcpu_t *vcpu)
@@ -1529,8 +1521,7 @@ static void fill_common_vmcs(struct vcpu_t *vcpu)
     vmwrite(vcpu, VMX_EXIT_MSR_STORE_ADDRESS, 0);
 
     vmwrite(vcpu, VMX_EXIT_MSR_LOAD_COUNT, 0);
-    vmwrite(vcpu, VMX_EXIT_MSR_LOAD_ADDRESS,
-            (uint64_t)hax_pa(cpu_data->hstate.hmsr_autoload));
+    vmwrite(vcpu, VMX_EXIT_MSR_LOAD_ADDRESS, 0);
 
     vmwrite(vcpu, VMX_ENTRY_INTERRUPT_INFO, 0);
     // vmwrite(NULL, VMX_ENTRY_EXCEPTION_ERROR_CODE, 0);