Add porting rule for assert 0;

py/dml/ctree.py

@@ -984,10 +984,15 @@ def as_bool(e):
     if isinstance(t, TBool):
         return e
     elif t.is_int and t.bits == 1:
-        if logging.show_porting and (isinstance(e, NodeRef)
-                                     or isinstance(e, LocalVariable)):
-            report(PBITNEQ(dmlparse.start_site(e.site),
-                           dmlparse.end_site(e.site)))
+        if logging.show_porting:
+            if e.constant:
+                report(PZEROCOND(dmlparse.start_site(e.site),
+                                 dmlparse.end_site(e.site),
+                                 'true' if e.value else 'false'))
+            elif (isinstance(e, NodeRef)
+                  or isinstance(e, LocalVariable)):
+                report(PBITNEQ(dmlparse.start_site(e.site),
+                               dmlparse.end_site(e.site)))
         return mkFlag(e.site, e)
     elif isinstance(t, TPtr):
         return mkNotEquals(e.site, e,

py/dml/messages.py

@@ -2346,6 +2346,11 @@ class PBITNEQ(PortingMessage):
     field values are 64 bit, and thus require an explicit `!= 0`"""
     fmt = ""
 
+class PZEROCOND(PortingMessage):
+    """DML 1.2 permits using the literals `0` and `1` as booleans. In DML 1.4,
+    this should be replaced with `false` and `true`, respectively"""
+    fmt = ""
+
 class PVAL(PortingMessage):
     """The value of a `register`, `field` or `attribute`
     object, and the interface struct of a `interface` object, is now

py/port_dml.py

@@ -802,6 +802,10 @@ def apply(self, f):
         start_offs = self.offset(f)
         [end_site] = self.params
         end_offs = self.offset(f, end_site)
+        self.insert_zero_compare(f, start_offs, end_offs)
+
+    @staticmethod
+    def insert_zero_compare(f, start_offs, end_offs):
         (pad, token, kind) = next(f.read_tokens(end_offs))
         from dml import dmllex14
         if kind in ('ID', 'RBRACKET', 'THIS', 'REGISTER', 'SIGNED',
@@ -817,6 +821,17 @@ def apply(self, f):
             # f => f != 0
             f.edit(end_offs, 0, ' != 0')
 
+class PZEROCOND(Transformation):
+    def apply(self, f):
+        start_offs = self.offset(f)
+        [end_site, value] = self.params
+        end_offs = self.offset(f, end_site)
+        (pad, token, kind) = next(f.read_tokens(end_offs))
+        if end_offs == start_offs and kind == 'ICONST':
+            f.edit(start_offs, token, value)
+        else:
+            PBITNEQ.insert_zero_compare(f, start_offs, end_offs)
+
 class PVAL(Transformation):
     # must happen after PBITNEQ
     phase = 1
@@ -1005,6 +1020,7 @@ def report(f, dest):
     'PIMPORT_DML12COMPAT': PIMPORT_DML12COMPAT,
     'PCHANGE_INARGS': PCHANGE_INARGS,
     'PBITNEQ': PBITNEQ,
+    'PZEROCOND': PZEROCOND,
     'PVAL': PVAL,
     'PNODOLLAR': PNODOLLAR,
     'PDOLLAR_QUALIFY': Replace,
@@ -1087,7 +1103,7 @@ def main(argv):
             already_added.add(key)
             t = tags[tag](loc, ast.literal_eval(params))
             transformations.setdefault(t.phase, []).append((t, lineno, line))
-        except:
+        except Exception:
             sys.stderr.write("Unexpected error on this porting tag:\n")
             sys.stderr.write(line)
             sys.stderr.write("%s:%d: found here\n" % (tagfilename, lineno))
@@ -1114,7 +1130,7 @@ def main(argv):
                     loc, '' if e.tag is None else ' ' + e.tag, e))
                 sys.stderr.write("%s:%d: found here\n" % (tagfilename, lineno))
                 errors += 1
-            except:
+            except Exception:
                 sys.stderr.write("Unexpected error on this porting tag:\n")
                 sys.stderr.write(line)
                 sys.stderr.write("%s:%d: found here\n" % (tagfilename, lineno))

test/1.2/misc/porting.dml

@@ -393,6 +393,8 @@ event ev2 is (evt) {
     parameter timebase = "seconds";
 }
 
+parameter zero = 0;
+
 method init() {
     local int1 i1;
 
@@ -428,4 +430,9 @@ method init() {
             $c.signal.signal_raise();
         }
     }
+    if (1) {
+        assert $zero;
+    } else {
+        assert 0;
+    }
 }

test/1.4/misc/porting.dml

@@ -418,6 +418,8 @@ template evt is event {
 event ev2 is (custom_time_event, evt) {
 }
 
+param zero = 0;
+
 method init() {
     local uint1 i1;
 
@@ -455,4 +457,9 @@ method init() {
             c.signal.signal_raise();
         }
     }
+    if (true) {
+        assert zero != 0;
+    } else {
+        assert false;
+    }
 }

test/tests.py

@@ -1388,6 +1388,7 @@ def test(self):
         'PABSTRACT_TEMPLATE',
         'PCHANGE_INARGS',
         'PBITNEQ',
+        'PZEROCOND',
         'PVAL',
         'PNODOLLAR',
         'PDOLLAR_QUALIFY',