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drm/panel: nt35510: move hardwired parameters to configuration
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This patch, preparatory for future developments, move the hardwired
parameters to configuration data to allow the addition of new
NT35510-based panels.

Signed-off-by: Dario Binacchi <[email protected]>
Reviewed-by: Linus Walleij <[email protected]>
Tested-by: Linus Walleij <[email protected]>
Signed-off-by: Linus Walleij <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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@passgat @linusw
passgat authored and linusw committed Jan 9, 2024
1 parent 9676bee commit 9b26d5c
Showing 1 changed file with 115 additions and 25 deletions.
140 changes: 115 additions & 25 deletions drivers/gpu/drm/panel/panel-novatek-nt35510.c
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Original file line number Diff line number Diff line change
Expand Up @@ -171,6 +171,10 @@ struct nt35510_config {
* timing in the display controller.
*/
const struct drm_display_mode mode;
/**
* @mode_flags: DSI operation mode related flags
*/
unsigned long mode_flags;
/**
* @avdd: setting for AVDD ranging from 0x00 = 6.5V to 0x14 = 4.5V
* in 0.1V steps the default is 0x05 which means 6.0V
Expand Down Expand Up @@ -273,6 +277,100 @@ struct nt35510_config {
* same layout of bytes as @vgp.
*/
u8 vgn[NT35510_P1_VGN_LEN];
/**
* @dopctr: setting optional control for display
* ERR bits 0..1 in the first byte is the ERR pin output signal setting.
* 0 = Disable, ERR pin output low
* 1 = ERR pin output CRC error only
* 2 = ERR pin output ECC error only
* 3 = ERR pin output CRC and ECC error
* The default is 0.
* N565 bit 2 in the first byte is the 16-bit/pixel format selection.
* 0 = R[4:0] + G[5:3] & G[2:0] + B[4:0]
* 1 = G[2:0] + R[4:0] & B[4:0] + G[5:3]
* The default is 0.
* DIS_EoTP_HS bit 3 in the first byte is "DSI protocol violation" error
* reporting.
* 0 = reporting when error
* 1 = not reporting when error
* DSIM bit 4 in the first byte is the video mode data type enable
* 0 = Video mode data type disable
* 1 = Video mode data type enable
* The default is 0.
* DSIG bit 5 int the first byte is the generic r/w data type enable
* 0 = Generic r/w disable
* 1 = Generic r/w enable
* The default is 0.
* DSITE bit 6 in the first byte is TE line enable
* 0 = TE line is disabled
* 1 = TE line is enabled
* The default is 0.
* RAMKP bit 7 in the first byte is the frame memory keep/loss in
* sleep-in mode
* 0 = contents loss in sleep-in
* 1 = contents keep in sleep-in
* The default is 0.
* CRL bit 1 in the second byte is the source driver data shift
* direction selection. This bit is XOR operation with bit RSMX
* of 3600h command.
* 0 (RMSX = 0) = S1 -> S1440
* 0 (RMSX = 1) = S1440 -> S1
* 1 (RMSX = 0) = S1440 -> S1
* 1 (RMSX = 1) = S1 -> S1440
* The default is 0.
* CTB bit 2 in the second byte is the vertical scanning direction
* selection for gate control signals. This bit is XOR operation
* with bit ML of 3600h command.
* 0 (ML = 0) = Forward (top -> bottom)
* 0 (ML = 1) = Reverse (bottom -> top)
* 1 (ML = 0) = Reverse (bottom -> top)
* 1 (ML = 1) = Forward (top -> bottom)
* The default is 0.
* CRGB bit 3 in the second byte is RGB-BGR order selection. This
* bit is XOR operation with bit RGB of 3600h command.
* 0 (RGB = 0) = RGB/Normal
* 0 (RGB = 1) = BGR/RB swap
* 1 (RGB = 0) = BGR/RB swap
* 1 (RGB = 1) = RGB/Normal
* The default is 0.
* TE_PWR_SEL bit 4 in the second byte is the TE output voltage
* level selection (only valid when DSTB_SEL = 0 or DSTB_SEL = 1,
* VSEL = High and VDDI = 1.665~3.3V).
* 0 = TE output voltage level is VDDI
* 1 = TE output voltage level is VDDA
* The default is 0.
*/
u8 dopctr[NT35510_P0_DOPCTR_LEN];
/**
* @madctl: Memory data access control
* RSMY bit 0 is flip vertical. Flips the display image top to down.
* RSMX bit 1 is flip horizontal. Flips the display image left to right.
* MH bit 2 is the horizontal refresh order.
* RGB bit 3 is the RGB-BGR order.
* 0 = RGB color sequence
* 1 = BGR color sequence
* ML bit 4 is the vertical refresh order.
* MV bit 5 is the row/column exchange.
* MX bit 6 is the column address order.
* MY bit 7 is the row address order.
*/
u8 madctl;
/**
* @sdhdtctr: source output data hold time
* 0x00..0x3F = 0..31.5us in steps of 0.5us
* The default is 0x05 = 2.5us.
*/
u8 sdhdtctr;
/**
* @gseqctr: EQ control for gate signals
* GFEQ_XX[3:0]: time setting of EQ step for falling edge in steps
* of 0.5us.
* The default is 0x07 = 3.5us
* GREQ_XX[7:4]: time setting of EQ step for rising edge in steps
* of 0.5us.
* The default is 0x07 = 3.5us
*/
u8 gseqctr[NT35510_P0_GSEQCTR_LEN];
/**
* @sdeqctr: Source driver control settings, first byte is
* 0 for mode 1 and 1 for mode 2. Mode 1 uses two steps and
Expand Down Expand Up @@ -536,46 +634,28 @@ static int nt35510_setup_display(struct nt35510 *nt)
{
struct mipi_dsi_device *dsi = to_mipi_dsi_device(nt->dev);
const struct nt35510_config *conf = nt->conf;
u8 dopctr[NT35510_P0_DOPCTR_LEN];
u8 gseqctr[NT35510_P0_GSEQCTR_LEN];
u8 dpfrctr[NT35510_P0_DPFRCTR1_LEN];
/* FIXME: set up any rotation (assume none for now) */
u8 addr_mode = NT35510_ROTATE_0_SETTING;
u8 val;
int ret;

/* Enable TE, EoTP and RGB pixel format */
dopctr[0] = NT35510_DOPCTR_0_DSITE | NT35510_DOPCTR_0_EOTP |
NT35510_DOPCTR_0_N565;
dopctr[1] = NT35510_DOPCTR_1_CTB;
ret = nt35510_send_long(nt, dsi, NT35510_P0_DOPCTR,
NT35510_P0_DOPCTR_LEN,
dopctr);
conf->dopctr);
if (ret)
return ret;

ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_ADDRESS_MODE, &addr_mode,
sizeof(addr_mode));
ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_ADDRESS_MODE, &conf->madctl,
sizeof(conf->madctl));
if (ret < 0)
return ret;

/*
* Source data hold time, default 0x05 = 2.5us
* 0x00..0x3F = 0 .. 31.5us in steps of 0.5us
* 0x0A = 5us
*/
val = 0x0A;
ret = mipi_dsi_dcs_write(dsi, NT35510_P0_SDHDTCTR, &val,
sizeof(val));
ret = mipi_dsi_dcs_write(dsi, NT35510_P0_SDHDTCTR, &conf->sdhdtctr,
sizeof(conf->sdhdtctr));
if (ret < 0)
return ret;

/* EQ control for gate signals, 0x00 = 0 us */
gseqctr[0] = 0x00;
gseqctr[1] = 0x00;
ret = nt35510_send_long(nt, dsi, NT35510_P0_GSEQCTR,
NT35510_P0_GSEQCTR_LEN,
gseqctr);
conf->gseqctr);
if (ret)
return ret;

Expand Down Expand Up @@ -896,7 +976,6 @@ static int nt35510_probe(struct mipi_dsi_device *dsi)
*/
dsi->hs_rate = 349440000;
dsi->lp_rate = 9600000;
dsi->mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS;

/*
* Every new incarnation of this display must have a unique
Expand All @@ -908,6 +987,8 @@ static int nt35510_probe(struct mipi_dsi_device *dsi)
return -ENODEV;
}

dsi->mode_flags = nt->conf->mode_flags;

nt->supplies[0].supply = "vdd"; /* 2.3-4.8 V */
nt->supplies[1].supply = "vddi"; /* 1.65-3.3V */
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(nt->supplies),
Expand Down Expand Up @@ -1030,6 +1111,7 @@ static const struct nt35510_config nt35510_hydis_hva40wv1 = {
.vtotal = 800 + 2 + 0 + 5, /* VBP = 5 */
.flags = 0,
},
.mode_flags = MIPI_DSI_CLOCK_NON_CONTINUOUS,
/* 0x09: AVDD = 5.6V */
.avdd = { 0x09, 0x09, 0x09 },
/* 0x34: PCK = Hsync/2, BTP = 2 x VDDB */
Expand All @@ -1050,6 +1132,14 @@ static const struct nt35510_config nt35510_hydis_hva40wv1 = {
.vgp = { 0x00, 0xA3, 0x00 },
/* VGMP: 0x0A3 = 5.0375V, VGSP = 0V */
.vgn = { 0x00, 0xA3, 0x00 },
/* Enable TE, EoTP and RGB pixel format */
.dopctr = { NT35510_DOPCTR_0_DSITE | NT35510_DOPCTR_0_EOTP |
NT35510_DOPCTR_0_N565, NT35510_DOPCTR_1_CTB },
.madctl = NT35510_ROTATE_0_SETTING,
/* 0x0A: SDT = 5 us */
.sdhdtctr = 0x0A,
/* EQ control for gate signals, 0x00 = 0 us */
.gseqctr = { 0x00, 0x00 },
/* SDEQCTR: source driver EQ mode 2, 2.5 us rise time on each step */
.sdeqctr = { 0x01, 0x05, 0x05, 0x05 },
/* SDVPCTR: Normal operation off color during v porch */
Expand Down

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