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Update IOMUXC enum variant documentation
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Briefly spot-checked the 1061 IOMUXC to make sure the diff of some
registers are correct. See the parent commit for context.
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@mciantyre
mciantyre committed Apr 6, 2024
1 parent 835fbfb commit 7a20156
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Showing 11 changed files with 479 additions and 477 deletions.
2 changes: 2 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -53,6 +53,8 @@ description, all lowercase). Dropping these fields changes the combiner's
approach for combining fieldsets, enabling correct documentation for non-
reserved fields.

Fix the documentation associated with IOMUXC field values.

## [0.5.0] 2022-12-27

Add support for NXP's i.MX RT 1176 dual-core MCUs. An `"imxrt1176_cm7"` feature
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8 changes: 4 additions & 4 deletions src/blocks/imxrt1015/iomuxc_gpr.rs
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Expand Up @@ -845,16 +845,16 @@ pub mod GPR2 {
}
#[doc = "GPR3 General Purpose Register"]
pub mod GPR3 {
#[doc = "Select 128-bit DCP key from 256-bit key from SNVS Master Key"]
#[doc = "Select 128-bit DCP key from 256-bit key from SNVS/OCOTP"]
pub mod DCP_KEY_SEL {
pub const offset: u32 = 4;
pub const mask: u32 = 0x01 << offset;
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select \\[127:0\\] from SNVS Master Key as DCP key"]
#[doc = "Select \\[127:0\\] from SNVS/OCOTP key as DCP key"]
pub const DCP_KEY_SEL_0: u32 = 0;
#[doc = "Select \\[255:128\\] from SNVS Master Key as DCP key"]
#[doc = "Select \\[255:128\\] from SNVS/OCOTP key as DCP key"]
pub const DCP_KEY_SEL_1: u32 = 0x01;
}
}
Expand Down Expand Up @@ -1871,7 +1871,7 @@ pub mod GPR10 {
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select key from SNVS Master Key."]
#[doc = "Select key from Key MUX (SNVS/OTPMK)."]
pub const DCPKEY_OCOTP_OR_KEYMUX_0: u32 = 0;
#[doc = "Select key from OCOTP (SW_GP2)."]
pub const DCPKEY_OCOTP_OR_KEYMUX_1: u32 = 0x01;
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2 changes: 1 addition & 1 deletion src/blocks/imxrt1015/iomuxc_snvs.rs
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Expand Up @@ -26,7 +26,7 @@ pub mod SW_MUX_CTL_PAD_PMIC_ON_REQ {
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp"]
pub const ALT0: u32 = 0;
#[doc = "Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5"]
#[doc = "Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5"]
pub const ALT5: u32 = 0x05;
}
}
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6 changes: 3 additions & 3 deletions src/blocks/imxrt1021/iomuxc.rs
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Expand Up @@ -2254,7 +2254,7 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_00 {
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_TMS of instance: jtag_mux"]
#[doc = "Select mux mode: ALT0 mux port: JTAG_TMS of instance: jtag_mux"]
pub const ALT0: u32 = 0;
#[doc = "Select mux mode: ALT5 mux port: GPIO1_IO00 of instance: gpio1"]
pub const ALT5: u32 = 0x05;
Expand Down Expand Up @@ -2285,7 +2285,7 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_01 {
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_TCK of instance: jtag_mux"]
#[doc = "Select mux mode: ALT0 mux port: JTAG_TCK of instance: jtag_mux"]
pub const ALT0: u32 = 0;
#[doc = "Select mux mode: ALT5 mux port: GPIO1_IO01 of instance: gpio1"]
pub const ALT5: u32 = 0x05;
Expand Down Expand Up @@ -2316,7 +2316,7 @@ pub mod SW_MUX_CTL_PAD_GPIO_AD_B0_02 {
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: JTAG_MUX_MOD of instance: jtag_mux"]
#[doc = "Select mux mode: ALT0 mux port: JTAG_MOD of instance: jtag_mux"]
pub const ALT0: u32 = 0;
#[doc = "Select mux mode: ALT5 mux port: GPIO1_IO02 of instance: gpio1"]
pub const ALT5: u32 = 0x05;
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24 changes: 12 additions & 12 deletions src/blocks/imxrt1021/iomuxc_gpr.rs
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Expand Up @@ -249,7 +249,7 @@ pub mod GPR1 {
pub mod RW {
#[doc = "OKAY response"]
pub const EXC_MON_0: u32 = 0;
#[doc = "SLVError response"]
#[doc = "SLVError response (default)"]
pub const EXC_MON_1: u32 = 0x01;
}
}
Expand All @@ -273,9 +273,9 @@ pub mod GPR1 {
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "AHB clock is not running (gated) when CM7 is sleeping and TCM is not accessible."]
#[doc = "AHB clock is not running (gated)"]
pub const CM7_FORCE_HCLK_EN_0: u32 = 0;
#[doc = "AHB clock is running (enabled) when CM7 is sleeping and TCM is accessible."]
#[doc = "AHB clock is running (enabled)"]
pub const CM7_FORCE_HCLK_EN_1: u32 = 0x01;
}
}
Expand All @@ -289,9 +289,9 @@ pub mod GPR2 {
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Enters power saving mode only when chip is in SUSPEND mode"]
#[doc = "none memory power saving features enabled, SHUTDOWN/DEEPSLEEP/LIGHTSLEEP will have no effect"]
pub const L2_MEM_EN_POWERSAVING_0: u32 = 0;
#[doc = "Controlled by L2_MEM_DEEPSLEEP bitfield"]
#[doc = "memory power saving features enabled, set SHUTDOWN/DEEPSLEEP/LIGHTSLEEP(priority high to low) to enable power saving levels"]
pub const L2_MEM_EN_POWERSAVING_1: u32 = 0x01;
}
}
Expand All @@ -315,9 +315,9 @@ pub mod GPR2 {
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "No force sleep control supported, memory deep sleep mode only entered when whole system in stop mode (OCRAM in normal mode)"]
#[doc = "no force sleep control supported, memory deep sleep mode only entered when whole system in stop mode"]
pub const L2_MEM_DEEPSLEEP_0: u32 = 0;
#[doc = "Force memory into deep sleep mode (OCRAM in power saving mode)"]
#[doc = "force memory into deep sleep mode"]
pub const L2_MEM_DEEPSLEEP_1: u32 = 0x01;
}
}
Expand Down Expand Up @@ -888,9 +888,9 @@ pub mod GPR2 {
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Timer counter works normally"]
#[doc = "timer counter work normally"]
pub const QTIMER1_TMR_CNTS_FREEZE_0: u32 = 0;
#[doc = "Reset counter and ouput flags"]
#[doc = "reset counter and ouput flags"]
pub const QTIMER1_TMR_CNTS_FREEZE_1: u32 = 0x01;
}
}
Expand Down Expand Up @@ -925,9 +925,9 @@ pub mod GPR3 {
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select \\[127:0\\] from SNVS Master Key as DCP key"]
#[doc = "Select \\[127:0\\] from snvs/ocotp key as dcp key"]
pub const DCP_KEY_SEL_0: u32 = 0;
#[doc = "Select \\[255:128\\] from SNVS Master Key as DCP key"]
#[doc = "Select \\[255:128\\] from snvs/ocotp key as dcp key"]
pub const DCP_KEY_SEL_1: u32 = 0x01;
}
}
Expand Down Expand Up @@ -2542,7 +2542,7 @@ pub mod GPR10 {
pub mod R {}
pub mod W {}
pub mod RW {
#[doc = "Select key from SNVS Master Key."]
#[doc = "Select key from Key MUX (SNVS/OTPMK)."]
pub const DCPKEY_OCOTP_OR_KEYMUX_0: u32 = 0;
#[doc = "Select key from OCOTP (SW_GP2)."]
pub const DCPKEY_OCOTP_OR_KEYMUX_1: u32 = 0x01;
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2 changes: 1 addition & 1 deletion src/blocks/imxrt1021/iomuxc_snvs.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -60,7 +60,7 @@ pub mod SW_MUX_CTL_PAD_PMIC_ON_REQ {
pub mod RW {
#[doc = "Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: snvs_lp"]
pub const ALT0: u32 = 0;
#[doc = "Select mux mode: ALT5 mux port: GPIO5_IO00 of instance: gpio5"]
#[doc = "Select mux mode: ALT5 mux port: GPIO5_IO01 of instance: gpio5"]
pub const ALT5: u32 = 0x05;
}
}
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