Chipathon2024 saltychip #347
Conversation
…m in Chipathon 2024
Developer: SaltyChip team in Chipathon 2024
|
Can you please convert this to a draft PR is work is yet to be completed? |
|
This work is not completed yet, so we converted this pull request to a draft. |
…cal layout (form of parallel-gate transistors)
…f the TG's PMOS and NMOS Next step: to add the I/O ports for the upcoming LVS work
…te's GDSII image, according to the main layout work in "transmission_gate.py" and "eval.py".
|
Hey guys, thanks for the contribution please check out |
Fix the DRC error by removing the deep N-well on the NMOS of the inv cell which
is used as the control component for the underlying transmission gate
Modify the PCell of the transmission gate composed of a basic TG cell and INV cell. The Magis DRC per basic cell and that of the top-level block have been performed w/o error
Modify the layout of both transmission gate and inverter
in a interdititized fashion so as to contruct a CDAC switch
Status: W.I.P.
:
Complete the first prototyping layout of the transmission gate in an interdigitized fashion
#Status:Magic DRC passed, netlist generation for the LVS is still working in progress
#PCell status: W.I.P.
#User manual about the PCell: W.I.P.
#Completion date (expected): 23.Nov.2024
Add the directory of building the layout of transmission-gate PCell
with GDS, Magic DRC and LVS results
|
We have added our working directory of the transmission gate, so we would like make a pull request for the PR draft of our work. Layout generated by using glayoutThree GDS of PCell layout is generated as depicted below.
Progress
Failed LVS report (corresponded to the design of W/L=12 um / 0.15 um) |
| model_pmos = pdk.models['pfet'] | ||
| model_nmos = pdk.models['nfet'] | ||
| print(f"model_pmos: {model_pmos}") | ||
| source_netlist = """.subckt {circuit_name} {nodes} """ + f'l={length} w={width} m={mtop} ' + """ |
There was a problem hiding this comment.
You do not need to write the spice for the netlist. It can be constructed using the spice of the sub-devices (FETs). Refer to
There was a problem hiding this comment.
We have rewritten the function to generate the SPICE netlist and got LVS passed for the transmission gate Pcell. The revision is shown on the commit: d9c2346
|
@tsengs0 did you make the changes requested in the previous review? It was marked as resolved but no commit was pushed. |
Sorry, I forgot to request a change. I will commit and push our latest revision by this week. |
1) Modify the transmission gate Pcell and its netlist generation for DRC free and LVS free
2) Create the Pcell layout of the 1-bit CDAC switch and 6-bit
3) Create the Pcell layout of the MIM capacitor array (not programmable/parameterisable yet)
Status:
1) Transmission gate Pcell: DRC free, LVS free
1.a) DRC free
1.b) LVS free
1.c) Testbench for post-layout simulation: W.I.P.
2) 1-bit CDAC switch Pcell
2.a) DRC free
2.b) LVS free
2.c) Testbench for post-layout simulation: W.I.P.
3) MIM capacitor array
3.a) DRC free
3.b) LVS: W.I.P.
4) 6-bit capacitive DAC: T.B.D.
|
Really sorry for late update since we were struggling with the LVS error for a long time. But now we can successfully pass LVS In our latest update, we separate our work into two directries: The first folder contributes the transmission gate Pcell where both DRC and LVS check are passed, and we are going to build the testbech for the post-layout simulation. On the other hand, the second folder is to generate the layout of the 1-bit CDAC switch, MIM capacitor array and 6-bit capacitive DAC (as the top level of our team's final output). So far, we only complete the layout of 1-bit CDAC switch with DRC and LVS free. |
Current progress of the team SaltyChip