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Initial upload of PGXP.
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@iCatButler
iCatButler committed Mar 25, 2016
1 parent 106f659 commit 7767ea4
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Showing 19 changed files with 727 additions and 51 deletions.
2 changes: 2 additions & 0 deletions libpcsxcore/gpu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -19,6 +19,7 @@
#include "psxhw.h"
#include "gpu.h"
#include "psxdma.h"
#include "pgxp_gte.h"

#define GPUSTATUS_ODDLINES 0x80000000
#define GPUSTATUS_DMABITS 0x60000000 // Two bits
Expand Down Expand Up @@ -142,6 +143,7 @@ void psxDma2(u32 madr, u32 bcr, u32 chcr) { // GPU
#endif
break;
}
GPU_pgxpMemory(madr, PGXP_GetMem());
GPU_writeDataMem(ptr, size);

#if 0
Expand Down
31 changes: 19 additions & 12 deletions libpcsxcore/gte.c
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Original file line number Diff line number Diff line change
Expand Up @@ -7,6 +7,7 @@

#include "gte.h"
#include "psxmem.h"
#include "pgxp_gte.h"

#define GTE_SF(op) ((op >> 19) & 1)
#define GTE_MX(op) ((op >> 17) & 3)
Expand Down Expand Up @@ -251,6 +252,7 @@ static void CTC2(u32 value, int reg) {
void gteMFC2() {
if (!_Rt_) return;
psxRegs.GPR.r[_Rt_] = MFC2(_Rd_);
PGXP_MFC2(_Rt_, _Rd_, psxRegs.CP2D.p[_Rd_].d);
}

void gteCFC2() {
Expand All @@ -259,6 +261,7 @@ void gteCFC2() {
}

void gteMTC2() {
PGXP_MTC2(_Rt_, _Rd_, psxRegs.GPR.p[_Rt_].d);
MTC2(psxRegs.GPR.r[_Rt_], _Rd_);
}

Expand All @@ -269,11 +272,15 @@ void gteCTC2() {
#define _oB_ (psxRegs.GPR.r[_Rs_] + _Imm_)

void gteLWC2() {
MTC2(psxMemRead32(_oB_), _Rt_);
u32 val = psxMemRead32(_oB_);
PGXP_LWC2(_oB_, _Rt_, val);
MTC2(val, _Rt_);
}

void gteSWC2() {
psxMemWrite32(_oB_, MFC2(_Rt_));
u32 val = MFC2(_Rt_);
PGXP_SWC2(_oB_, _Rt_, val);
psxMemWrite32(_oB_, val);
}

inline s64 gte_shift(s64 a, int sf) {
Expand Down Expand Up @@ -490,10 +497,9 @@ int docop2(int op) {
SX2 = Lm_G1(F((s64) OFX + ((s64) IR1 * h_over_sz3) * (Config.Widescreen ? 0.75 : 1)) >> 16);
SY2 = Lm_G2(F((s64) OFY + ((s64) IR2 * h_over_sz3)) >> 16);

GPU_addVertex(SX2, SY2,
Lm_G1_ia((s64) OFX + (s64)(IR1 * h_over_sz3) * (Config.Widescreen ? 0.75 : 1)),
Lm_G2_ia((s64) OFY + (s64)(IR2 * h_over_sz3)),
((s64)SZ3));
PGXP_pushSXYZ2s(Lm_G1_ia((s64)OFX + (s64)(IR1 * h_over_sz3) * (Config.Widescreen ? 0.75 : 1)),
Lm_G2_ia((s64)OFY + (s64)(IR2 * h_over_sz3)),
SZ3);

MAC0 = F((s64) DQB + ((s64) DQA * h_over_sz3));
IR0 = Lm_H(m_mac0, 1);
Expand All @@ -503,8 +509,10 @@ int docop2(int op) {
#ifdef GTE_LOG
GTELOG("%08x NCLIP", op);
#endif

MAC0 = F((s64) (SX0 * SY1) + (SX1 * SY2) + (SX2 * SY0) - (SX0 * SY2) - (SX1 * SY0) - (SX2 * SY1));
if (PGXP_NLCIP_valid())
MAC0 = F(PGXP_NCLIP());
else
MAC0 = F((s64) (SX0 * SY1) + (SX1 * SY2) + (SX2 * SY0) - (SX0 * SY2) - (SX1 * SY0) - (SX2 * SY1));
return 1;

case 0x0c:
Expand Down Expand Up @@ -879,10 +887,9 @@ int docop2(int op) {
SX2 = Lm_G1(F((s64) OFX + ((s64) IR1 * h_over_sz3) * (Config.Widescreen ? 0.75 : 1)) >> 16);
SY2 = Lm_G2(F((s64) OFY + ((s64) IR2 * h_over_sz3)) >> 16);

GPU_addVertex(SX2, SY2,
Lm_G1_ia((s64) OFX + (s64)(IR1 * h_over_sz3) * (Config.Widescreen ? 0.75 : 1)),
Lm_G2_ia((s64) OFY + (s64)(IR2 * h_over_sz3)),
((s64)SZ3));
PGXP_pushSXYZ2s(Lm_G1_ia((s64)OFX + (s64)(IR1 * h_over_sz3) * (Config.Widescreen ? 0.75 : 1)),
Lm_G2_ia((s64)OFY + (s64)(IR2 * h_over_sz3)),
SZ3);
}

MAC0 = F((s64) DQB + ((s64) DQA * h_over_sz3));
Expand Down
47 changes: 29 additions & 18 deletions libpcsxcore/ix86/iR3000A.c
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Original file line number Diff line number Diff line change
Expand Up @@ -25,6 +25,7 @@

#include "ix86.h"
#include <sys/mman.h>
#include "pgxp_gte.h"

#ifndef MAP_ANONYMOUS
#define MAP_ANONYMOUS MAP_ANON
Expand Down Expand Up @@ -1546,14 +1547,15 @@ static void recLW() {
// SysPrintf("unhandled r32 %x\n", addr);
}

PUSH32I(psxRegs.code); // iCB: Needed to extract reg and opcode
iPushOfB();
CALLFunc((u32)psxMemRead32);
CALLFunc((u32)PGXP_psxMemRead32Trace);
if (_Rt_) {
iRegs[_Rt_].state = ST_UNK;
MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
}
// ADD32ItoR(ESP, 4);
resp+= 4;
resp+= 8;
}

extern u32 LWL_MASK[4];
Expand Down Expand Up @@ -1601,12 +1603,13 @@ void recLWL() {
if (_Imm_) ADD32ItoR(EAX, _Imm_);
}
PUSH32R (EAX);
PUSH32I(psxRegs.code); // iCB: Needed to extract reg and opcode
AND32ItoR(EAX, ~3);
PUSH32R (EAX);
CALLFunc((u32)psxMemRead32);
CALLFunc((u32)PGXP_psxMemRead32Trace);

if (_Rt_) {
ADD32ItoR(ESP, 4);
ADD32ItoR(ESP, 8);
POP32R (EDX);
AND32ItoR(EDX, 0x3); // shift = addr & 3;

Expand All @@ -1629,7 +1632,7 @@ void recLWL() {
MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
} else {
// ADD32ItoR(ESP, 8);
resp+= 8;
resp+= 12;
}
}

Expand Down Expand Up @@ -1756,12 +1759,13 @@ void recLWR() {
if (_Imm_) ADD32ItoR(EAX, _Imm_);
}
PUSH32R (EAX);
PUSH32I(psxRegs.code); // iCB: Needed to extract reg and opcode
AND32ItoR(EAX, ~3);
PUSH32R (EAX);
CALLFunc((u32)psxMemRead32);
CALLFunc((u32)PGXP_psxMemRead32Trace);

if (_Rt_) {
ADD32ItoR(ESP, 4);
ADD32ItoR(ESP, 8);
POP32R (EDX);
AND32ItoR(EDX, 0x3); // shift = addr & 3;

Expand All @@ -1785,7 +1789,7 @@ void recLWR() {
MOV32RtoM((u32)&psxRegs.GPR.r[_Rt_], EAX);
} else {
// ADD32ItoR(ESP, 8);
resp+= 8;
resp+= 12;
}
}

Expand Down Expand Up @@ -1978,15 +1982,16 @@ static void recSW() {
// SysPrintf("unhandled w32 %x\n", addr);
}

PUSH32I(psxRegs.code); // iCB: Needed to extract reg and opcode
if (IsConst(_Rt_)) {
PUSH32I (iRegs[_Rt_].k);
} else {
PUSH32M ((u32)&psxRegs.GPR.r[_Rt_]);
}
iPushOfB();
CALLFunc((u32)psxMemWrite32);
CALLFunc((u32)PGXP_psxMemWrite32Trace);
// ADD32ItoR(ESP, 8);
resp+= 8;
resp+= 12;
}
//#endif

Expand Down Expand Up @@ -2104,12 +2109,13 @@ void recSWL() {
if (_Imm_) ADD32ItoR(EAX, _Imm_);
}
PUSH32R (EAX);
PUSH32I(psxRegs.code); // iCB: Needed to extract reg and opcode
AND32ItoR(EAX, ~3);
PUSH32R (EAX);

CALLFunc((u32)psxMemRead32);
CALLFunc((u32)PGXP_psxMemRead32Trace);

ADD32ItoR(ESP, 4);
ADD32ItoR(ESP, 8);
POP32R (EDX);
AND32ItoR(EDX, 0x3); // shift = addr & 3;

Expand All @@ -2126,6 +2132,8 @@ void recSWL() {
}
SHR32CLtoR(EDX); // _rRt_ >> SWL_SHIFT[shift]

PUSH32I(psxRegs.code); // iCB: Needed to extract reg and opcode

OR32RtoR (EAX, EDX);
PUSH32R (EAX);

Expand All @@ -2137,9 +2145,9 @@ void recSWL() {
AND32ItoR(EAX, ~3);
PUSH32R (EAX);

CALLFunc((u32)psxMemWrite32);
CALLFunc((u32)PGXP_psxMemWrite32Trace);
// ADD32ItoR(ESP, 8);
resp+= 8;
resp+= 12;
}

extern u32 SWR_MASK[4];
Expand Down Expand Up @@ -2186,12 +2194,13 @@ void recSWR() {
if (_Imm_) ADD32ItoR(EAX, _Imm_);
}
PUSH32R (EAX);
PUSH32I(psxRegs.code); // iCB: Needed to extract reg and opcode
AND32ItoR(EAX, ~3);
PUSH32R (EAX);

CALLFunc((u32)psxMemRead32);
CALLFunc((u32)PGXP_psxMemRead32Trace);

ADD32ItoR(ESP, 4);
ADD32ItoR(ESP, 8);
POP32R (EDX);
AND32ItoR(EDX, 0x3); // shift = addr & 3;

Expand All @@ -2208,6 +2217,8 @@ void recSWR() {
}
SHL32CLtoR(EDX); // _rRt_ << SWR_SHIFT[shift]

PUSH32I(psxRegs.code); // iCB: Needed to extract reg and opcode

OR32RtoR (EAX, EDX);
PUSH32R (EAX);

Expand All @@ -2219,9 +2230,9 @@ void recSWR() {
AND32ItoR(EAX, ~3);
PUSH32R (EAX);

CALLFunc((u32)psxMemWrite32);
CALLFunc((u32)PGXP_psxMemWrite32Trace);
// ADD32ItoR(ESP, 8);
resp += 8;
resp += 12;
}

/*REC_FUNC(SLL);
Expand Down
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