sc instruction: Make sure the rt register is mapped. Fixes Beats.

hrydgard · Sep 11, 2023 · accd9b1 · accd9b1
1 parent 57edb9f
commit accd9b1
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/Core/MIPS/x86/CompLoadStore.cpp b/Core/MIPS/x86/CompLoadStore.cpp
@@ -429,6 +429,7 @@ namespace MIPSComp {
 			skipStore = J_CC(CC_NE);
 
 			CompITypeMemWrite(op, 32, safeMemFuncs.writeU32);
+			gpr.MapReg(rt, true, true);
 			MOV(32, gpr.R(rt), Imm32(1));
 			finish = J();