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fix IR interpreter on big-endian machines.
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aliaspider committed May 5, 2018
1 parent 3ed4294 commit 0188d5c
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Showing 2 changed files with 20 additions and 18 deletions.
30 changes: 16 additions & 14 deletions Core/MIPS/IR/IRInterpreter.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -618,45 +618,47 @@ u32 IRInterpret(MIPSState *mips, const IRInst *inst, int count) {
case IROp::Mult:
{
s64 result = (s64)(s32)mips->r[inst->src1] * (s64)(s32)mips->r[inst->src2];
memcpy(&mips->lo, &result, 8);
mips->lo = (u32)result;
mips->hi = (u32)(result >> 32);
break;
}
case IROp::MultU:
{
u64 result = (u64)mips->r[inst->src1] * (u64)mips->r[inst->src2];
memcpy(&mips->lo, &result, 8);
mips->lo = (u32)result;
mips->hi = (u32)(result >> 32);
break;
}
case IROp::Madd:
{
s64 result;
memcpy(&result, &mips->lo, 8);
s64 result = (s64)((u64)mips->lo | ((u64)mips->hi << 32));
result += (s64)(s32)mips->r[inst->src1] * (s64)(s32)mips->r[inst->src2];
memcpy(&mips->lo, &result, 8);
mips->lo = (u32)result;
mips->hi = (u32)(result >> 32);
break;
}
case IROp::MaddU:
{
s64 result;
memcpy(&result, &mips->lo, 8);
s64 result = (s64)((u64)mips->lo | ((u64)mips->hi << 32));
result += (u64)mips->r[inst->src1] * (u64)mips->r[inst->src2];
memcpy(&mips->lo, &result, 8);
mips->lo = (u32)result;
mips->hi = (u32)(result >> 32);
break;
}
case IROp::Msub:
{
s64 result;
memcpy(&result, &mips->lo, 8);
s64 result = (s64)((u64)mips->lo | ((u64)mips->hi << 32));
result -= (s64)(s32)mips->r[inst->src1] * (s64)(s32)mips->r[inst->src2];
memcpy(&mips->lo, &result, 8);
mips->lo = (u32)result;
mips->hi = (u32)(result >> 32);
break;
}
case IROp::MsubU:
{
s64 result;
memcpy(&result, &mips->lo, 8);
s64 result = (s64)((u64)mips->lo | ((u64)mips->hi << 32));
result -= (u64)mips->r[inst->src1] * (u64)mips->r[inst->src2];
memcpy(&mips->lo, &result, 8);
mips->lo = (u32)result;
mips->hi = (u32)(result >> 32);
break;
}

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8 changes: 4 additions & 4 deletions Core/MemMap.h
Original file line number Diff line number Diff line change
Expand Up @@ -189,9 +189,9 @@ inline u32 ReadUnchecked_U32(const u32 address) {

inline float ReadUnchecked_Float(const u32 address) {
#ifdef MASKED_PSP_MEMORY
return *(float *)(base + (address & MEMVIEW32_MASK));
return *(float_le *)(base + (address & MEMVIEW32_MASK));
#else
return *(float *)(base + address);
return *(float_le *)(base + address);
#endif
}

Expand Down Expand Up @@ -221,9 +221,9 @@ inline void WriteUnchecked_U32(u32 data, u32 address) {

inline void WriteUnchecked_Float(float data, u32 address) {
#ifdef MASKED_PSP_MEMORY
*(float *)(base + (address & MEMVIEW32_MASK)) = data;
*(float_le *)(base + (address & MEMVIEW32_MASK)) = data;
#else
*(float *)(base + address) = data;
*(float_le *)(base + address) = data;
#endif
}

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