Default Logic Mapping
| Bit | Signal | Input | Z80 | Colour |
|---|---|---|---|---|
| 0 | D0 | PB0 | 14 | Black |
| 1 | D1 | PB1 | 15 | Brown |
| 2 | D2 | PB2 | 12 | Red |
| 3 | D3 | PB3 | 8 | Orange |
| 4 | D4 | PB4 | 7 | Yellow |
| 5 | D5 | PB5 | 9 | Green |
| 6 | D6 | PB6 | 10 | Blue |
| 7 | D7 | PB7 | 13 | Violet |
| 8 | /M1 | PD0 | 27 | White |
| 9 | /RD | PD1 | 21 | Grey |
| 10 | /WR | PD2 | 22 | Violet |
| 11 | /MREQ | PD3 | 19 | Blue |
| 12 | /IORQ | PD4 | 20 | Green |
| 13 | /WAIT | PD5 | 24 | Yellow |
| 14 | /RST | PD6 | 26 | Orange |
| 15 | (CLK) | PD7 | 6 | - |
There are command-line options to change these, but above are the recommended defaults, this makes exchanging files easier.
(WAIT is only really needed to get accurate cycle counts)
If you are using synchronous capture mode, use the rising edge of CLK to take a sample, and include the --phi= argument (with no number) on the decoder command line.
If you are using asynchronous capture mode, this needs to be at least 5x the system clock rate, ideally 10x. In this case, connect CLK to Logic Analyzer Bit 15.