Circuit with random start and how to avoid ?

[jongena]

I have the following circuit: a clock (with two phase output ΦC and ΦT ) and two connected D-flip-flops using each as clock input the
inversion of one of the phases (see attached)
The ouputs of the second D-flip flop look random at the start of the circuit. Sometimes it starts with output 2 high and output 3 low
and sometimes it is the reverse. Output 1 on the other hand is always the same. See attached output files.

I also constructed a 16 bit shift register, with 16 consecutive D flip flops (again with inverted C input) showing similar effects.
Another side effect seems to be that the D input is immediately visible at the output, thus overwriting the default output.

Further tests showed that when the inversion is removed at the C input, the random behaviour disappeared, and also the default output then appeared on the Q output.

My question is how this effect with the inverted C input should be understood, and equally important, what can be done to assure that only one of the two options will be output at the start of the simulation when the inverted C input is in use?

Shift registers of various lengths with consecutive D flip flops are used in the circuit I have at hand and determine the state of other ones. The seemingly random starting conditions (as seen in one of the photos with the traces) set the whole circuit in a random state at the beginning of the simulation.

From what I have seen in Digital over the past months, it is a very powerful tool, so I am sure that there must be a way to tackle this.
My questions:

1. How to make sure that always only one of the two possible initial states will appear ? Is there a way to force the Digital simulation to always start in exactly the same way ?
2. Is there a perhaps better way to implement a shift register than with consecutive D flip-flops ?

Am I making an elephant out of a fly ... ? Perhaps... but as a novice in this field I am still learning every day !
Any hint is very welcome.

[hneemann]

You can use the reset component to ensure that the circuit always starts in the same way.
In general, it is bad practice to generate the clock signal of a component by logic gates.
It is better to use a common clock signal for all flip-flops.

[jongena]

I continued my tests. I keep having random output using the standard D flip-flops of Digital. So I replaced all "two phase clock" D flip-flops using registers and the enabling option with the reset component. This leads indeed to a standard start, which is excellent ! The only problem that remains is that I need to set the output of these custom "two phase clock" D flip-flips to default high (because of the negative logic). I get otherwise conflicting conditions at the start of the simulation. From what I understand this seems to come down to set the default output of the register to high. However, I do not see a direct possibility to do so.

Q1: Is there a way to enforce a positive Q output as a default for the register (or perhaps, more in general, enforcing default outputs to custom components) ?
Q2: the best solution still (because of additional delays that otherwise need to be corrected throughout the simulation) seems to be able to use the standard D flip-flop of DIgital, but then such that it always start in the same way. Any possibility to do this with the reset component ?
Q3: I also built D flip-flops as custom components ("using crossed gates"), with the reset component inside to define "Q = high" as the default output. But these custom components do not behave exactly as the standard D flip flop of Digital: the Q and ~Q outputs have a small phase where they are at the same logical level; with the standard D flip-flop the Q and ~Q outputs are always exactly opposite to each other. This small phase where Q and ~Q are at the same level leads to "oscillation errors" in other parts of the simulation.

How to proceed here without having to revise the whole simulation... (thereby avoiding all kinds of other difficulties...) ?
To my opinion, the best would be to use the standard D- flip flops in Digital, but with the possibility to use the reset component, to avoid random outputs at the start.

Of course, any other suggestion is welcome.... to arrive at both (i) a stable start of the simulation using the reset component (or by any other means) and (ii) with "high" as a default for the Q output of the D-flip-flop, register, any other (custom) component that could be suitable, or an additional circuit that helps to realize this double requirement.

Any advice is highly welcome.

[jongena]

Continuing the investigations, here is what I think is the best solution for the D flip flop that I need: using an asynchronous D flip flop combined with the reset component, as per the circuit below. I implemented it, and seems to realize the two conditions above: I now get a unique starting point at the start of the simulation, with the Q output at high level.
Let me know if this could be realized even simpler ?

[hneemann]

@jongena
That's a pretty good idea! I'm surprised I didn't come up with it myself, because that's exactly how you would build it with real hardware. Especially considering that a similar implementation has already been proposed here at some point, but I can't find the old issue:

Using the asynchronous flip-flop makes the circuit much simpler, of course.

[jnoche]

"I can't find the old issue." Are you referring to #1028 ?

[hneemann]

@jnoche
Yes! Thank you!