Strider: Signal Value Transition-Guided Defect Repair for HDL Programming Assignments

• Strider: Signal Value Transition-Guided Defect Repair for HDL Programming Assignments
  • 1. Strider Framework
  • 2. Reproduction
    • 2.1. Downloading the Repository
    • 2.2. Configuration
    • 2.3. Execution
  • 3. Structure
  • 4. LICENSE

This repository consits of all relevant artifacts of Strider.

1. Strider Framework

The framework of Strider is present as follows:

We aim to contribute an APR technique toward Verilog programs that leverages signal value transition. We release the complete source code Strider that covers the whole automated defect repair pipeline, including defect localization, patch synthesis and patch validation. We hope the publicly available implementation could facilitate follow-up research towards hardware deisign code.

2. Reproduction

2.1. Downloading the Repository

Use the following command to download the artifact repository:

git clone --recursive [email protected]:hejy47/Strider.git

2.2. Configuration

To run Strider, you will need to compile Pyverilog if you have not done so already:

make

And instanll the following python packages

pip install dataclasses PyVCD

Configure the cirfix_benchmarks and Assignment4V dataset:

cd benchmarks;
unzip cirfix_benchmarks;
git clone https://github.com/hejy47/Assignment4V.git dataset_Assignment4V
cp dataset_Assignment4V/dataset/* ./

We use the following tools for compilation and simulation of Verilog code:

• Icarus Verilog: sudo apt-get install iverilog (for Ubuntu)
• Synopsys VCS (Commercial license)

2.3. Execution

Our prototype of Strider needs three input options for execution:

• --benchmark/-b: the benchmark name. (cirfix_benchmarks for the example)
• --project/-p: the project name of defective program of the benchmakr. (fsm_full for the example)
• --version/-v: the identifier of the defective program. (1 for the example)

Example: python strider/Main.py -b cirfix_benchmarks -p fsm_full -v 1

3. Structure

STRIDER
├── benchmarks
│   ├── Assignment4V:          data directory of Assignment4V
│   ├── Assignment4V.conf:     configuration file of Assignment4V
│   ├── cirfix_benchmarks:      data directory of cirfix_benchmarks
│   └── cirfix_benchmarks.conf: configuration file of cirfix_benchmarks
├── doc
│   └── figs:                   figure of Strider framework
├── libs
│   └── Pyverilog
├── logs
├── patch
│   ├── Assignment4V:          patches generated by Strider for Assignment4V
│   └── cirfix_benchmarks:      patches generated by Strider for cirfix_benchmarks
└── strider:                    source code of Strider
    ├── Adapter
    ├── Benchmark
    ├── Locator
    ├── utils
    ├── VerilogAnalyzer
    ├── Main.py
    ├── Repair.py
    └── Config.py

P.S. The dataset of cirfix_benchmarks is from the benchmark of CirFix

4. LICENSE

The repository is licensed under the GNU GPLv3 license. See LICENSE for details.