Only catch up when setting CHR banks

hcs64 · May 20, 2024 · 0575216 · 0575216
1 parent a15a647
commit 0575216
Showing 1 changed file with 20 additions and 10 deletions.
diff --git a/src/mappers/mapper4.asm b/src/mappers/mapper4.asm
@@ -128,16 +128,6 @@ if {defined LOG_MMC3} {
   addi sp, -8
 }
 
-  lw t1, ppu_catchup_cb (r0)
-  // delay slot?
-  beqz t1,+
-  nop // delay slot?
-  sw ra, cpu_rw_handler_ra (r0)
-  jalr t1
-  nop
-  lw ra, cpu_rw_handler_ra (r0)
-+
-
   andi t0, cpu_t1, 0b0110'0000'0000'0000
   andi t1, cpu_t1, 1
   srl t0, 13-1
@@ -278,6 +268,16 @@ mmc3_prgrom_update_done:
   nop
 
 macro mmc3_map_2k_chr(page_addr) {
+    lw t1, ppu_catchup_cb (r0)
+    // delay slot?
+    beqz t1,+
+    nop // delay slot?
+    sw ra, cpu_rw_handler_ra (r0)
+    jalr t1
+    nop
+    lw ra, cpu_rw_handler_ra (r0)
++
+
     ls_gp(lw t0, chrrom_start)
     ls_gp(lwu t2, chrrom_mask)
     andi t1, cpu_t0, 0b1111'1110 // low bit unused
@@ -290,6 +290,16 @@ macro mmc3_map_2k_chr(page_addr) {
     sw t0, ppu_map + {page_addr}/0x400*4+4 (r0)
 }
 macro mmc3_map_1k_chr(page_addr) {
+    lw t1, ppu_catchup_cb (r0)
+    // delay slot?
+    beqz t1,+
+    nop // delay slot?
+    sw ra, cpu_rw_handler_ra (r0)
+    jalr t1
+    nop
+    lw ra, cpu_rw_handler_ra (r0)
++
+
     ls_gp(lw t0, chrrom_start)
     ls_gp(lwu t2, chrrom_mask)
     sll t1, cpu_t0, mmc3_chrrom_page_shift