UT_Computer_Architecture

I prepared these files as my assignments during the Computer Architecture course at School of Electrical and Computer Engineering, University College of Engineering, University of Tehran. I took this course during my fifth B.Sc. semester (Fall 2021).

What do they include?

The first computer assignment (CA) is writing a SystemVerilog model of an RTL design which does a restoring division algorithm.

The second and fourth CA are the SystemVerilog codes for a single-cycle and a pipelined MIPS processor respectively, only supporting some of the complete MIPS commands.

The third CAs is coding a processor, which we believe is inspired by ARM.

By who?

Done by Mohammad Mahdi Moeini Manesh and me.

How much did these projects score?

CA2 scored 110/100 (worked without bugs)

CA3 scored 85/100 (had a bug)

CA4 scored 103/100 (worked without bugs)

What is this language in the PDFs? Is it Arabic?

No, it's Persian. Maybe I'll translate them into English one day.