Merge branch 'main' into fixes

grumpycoders · Nov 22, 2024 · 82e6a44 · 82e6a44
2 parents d22386c + 4869d30
commit 82e6a44
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Showing 127 changed files with 1,373 additions and 687 deletions.
diff --git a/src/cdrom/cdriso.cc b/src/cdrom/cdriso.cc
@@ -248,10 +248,12 @@ uint8_t *PCSX::CDRIso::getBuffer() {
 
 void PCSX::CDRIso::printTracks() {
     for (int i = 1; i <= m_numtracks; i++) {
-        PCSX::g_system->printf(
-            _("Track %.2d (%s) - Start %.2d:%.2d:%.2d, Length %.2d:%.2d:%.2d\n"), i,
-            (m_ti[i].type == TrackType::DATA ? "DATA" : m_ti[i].cddatype == trackinfo::CCDDA ? "CZDA" : "CDDA"),
-            m_ti[i].start.m, m_ti[i].start.s, m_ti[i].start.f, m_ti[i].length.m, m_ti[i].length.s, m_ti[i].length.f);
+        PCSX::g_system->printf(_("Track %.2d (%s) - Start %.2d:%.2d:%.2d, Length %.2d:%.2d:%.2d\n"), i,
+                               (m_ti[i].type == TrackType::DATA        ? "DATA"
+                                : m_ti[i].cddatype == trackinfo::CCDDA ? "CZDA"
+                                                                       : "CDDA"),
+                               m_ti[i].start.m, m_ti[i].start.s, m_ti[i].start.f, m_ti[i].length.m, m_ti[i].length.s,
+                               m_ti[i].length.f);
     }
 }
 

diff --git a/src/core/DynaRec_aa64/gte_aa64.cc b/src/core/DynaRec_aa64/gte_aa64.cc
@@ -21,8 +21,8 @@
 
 #if defined(DYNAREC_AA64)
 #include "core/gte.h"
-#define COP2_CONTROL_OFFSET(reg) ((uintptr_t)&m_regs.CP2C.r[(reg)] - (uintptr_t)this)
-#define COP2_DATA_OFFSET(reg) ((uintptr_t)&m_regs.CP2D.r[(reg)] - (uintptr_t)this)
+#define COP2_CONTROL_OFFSET(reg) ((uintptr_t) & m_regs.CP2C.r[(reg)] - (uintptr_t)this)
+#define COP2_DATA_OFFSET(reg) ((uintptr_t) & m_regs.CP2D.r[(reg)] - (uintptr_t)this)
 
 void DynaRecCPU::recCOP2(uint32_t code) {
     const auto func = m_recGTE[code & 0x3f];  // Look up the opcode in our decoding LUT

diff --git a/src/core/DynaRec_aa64/recompiler.cc b/src/core/DynaRec_aa64/recompiler.cc
@@ -304,9 +304,9 @@ DynarecCallback DynaRecCPU::recompile(DynarecCallback* callback, uint32_t pc, bo
         m_linkedPC = std::nullopt;
     }
 
-    gen.Ldr(w0, MemOperand(contextPointer, CYCLE_OFFSET));  // Fetch cycle count from memory
-    gen.Add(w0, w0, count * PCSX::Emulator::BIAS);          // Add block cycles
-    gen.Str(w0, MemOperand(contextPointer, CYCLE_OFFSET));  // Store cycles back to memory
+    gen.Ldr(x0, MemOperand(contextPointer, CYCLE_OFFSET));  // Fetch cycle count from memory
+    gen.Add(x0, x0, count * PCSX::Emulator::BIAS);          // Add block cycles
+    gen.Str(x0, MemOperand(contextPointer, CYCLE_OFFSET));  // Store cycles back to memory
 
     // Link block else return to dispatcher
     if (m_linkedPC && ENABLE_BLOCK_LINKING && m_linkedPC.value() != startingPC) {

diff --git a/src/core/DynaRec_aa64/recompiler.h b/src/core/DynaRec_aa64/recompiler.h
@@ -33,13 +33,13 @@
 #include "spu/interface.h"
 #include "tracy/public/tracy/Tracy.hpp"
 
-#define HOST_REG_CACHE_OFFSET(x) ((uintptr_t)&m_hostRegisterCache[(x)] - (uintptr_t)this)
-#define GPR_OFFSET(x) ((uintptr_t)&m_regs.GPR.r[(x)] - (uintptr_t)this)
-#define COP0_OFFSET(x) ((uintptr_t)&m_regs.CP0.r[(x)] - (uintptr_t)this)
-#define PC_OFFSET ((uintptr_t)&m_regs.pc - (uintptr_t)this)
-#define LO_OFFSET ((uintptr_t)&m_regs.GPR.n.lo - (uintptr_t)this)
-#define HI_OFFSET ((uintptr_t)&m_regs.GPR.n.hi - (uintptr_t)this)
-#define CYCLE_OFFSET ((uintptr_t)&m_regs.cycle - (uintptr_t)this)
+#define HOST_REG_CACHE_OFFSET(x) ((uintptr_t) & m_hostRegisterCache[(x)] - (uintptr_t)this)
+#define GPR_OFFSET(x) ((uintptr_t) & m_regs.GPR.r[(x)] - (uintptr_t)this)
+#define COP0_OFFSET(x) ((uintptr_t) & m_regs.CP0.r[(x)] - (uintptr_t)this)
+#define PC_OFFSET ((uintptr_t) & m_regs.pc - (uintptr_t)this)
+#define LO_OFFSET ((uintptr_t) & m_regs.GPR.n.lo - (uintptr_t)this)
+#define HI_OFFSET ((uintptr_t) & m_regs.GPR.n.hi - (uintptr_t)this)
+#define CYCLE_OFFSET ((uintptr_t) & m_regs.cycle - (uintptr_t)this)
 
 #undef _PC_
 #undef _Op_

diff --git a/src/core/DynaRec_x64/gte_x64.cc b/src/core/DynaRec_x64/gte_x64.cc
@@ -21,8 +21,8 @@
 
 #if defined(DYNAREC_X86_64)
 #include "core/gte.h"
-#define COP2_CONTROL_OFFSET(reg) ((uintptr_t)&m_regs.CP2C.r[(reg)] - (uintptr_t)this)
-#define COP2_DATA_OFFSET(reg) ((uintptr_t)&m_regs.CP2D.r[(reg)] - (uintptr_t)this)
+#define COP2_CONTROL_OFFSET(reg) ((uintptr_t) & m_regs.CP2C.r[(reg)] - (uintptr_t)this)
+#define COP2_DATA_OFFSET(reg) ((uintptr_t) & m_regs.CP2D.r[(reg)] - (uintptr_t)this)
 
 void DynaRecCPU::recCOP2(uint32_t code) {
     const auto func = m_recGTE[m_regs.code & 0x3F];  // Look up the opcode in our decoding LUT

diff --git a/src/core/DynaRec_x64/recompiler.cc b/src/core/DynaRec_x64/recompiler.cc
@@ -450,7 +450,7 @@ DynarecCallback DynaRecCPU::recompile(uint32_t pc, bool fullLoadDelayEmulation,
         endProfiling();
     }
 
-    gen.add(dword[contextPointer + CYCLE_OFFSET], count * PCSX::Emulator::BIAS);  // Add block cycles;
+    gen.add(qword[contextPointer + CYCLE_OFFSET], count * PCSX::Emulator::BIAS);  // Add block cycles;
     if (m_linkedPC && ENABLE_BLOCK_LINKING && m_linkedPC.value() != startingPC) {
         handleLinking();
     } else {
@@ -476,7 +476,7 @@ void DynaRecCPU::handleKernelCall() {
         return;
     }
 
-    const uint32_t pc = m_pc & 0x1fffff;
+    const uint32_t pc = m_pc & PCSX::g_emulator->getRamMask();
     const uint32_t base = (m_pc >> 20) & 0xffc;
     if ((base != 0x000) && (base != 0x800) && (base != 0xa00))
         return;  // Mask out the segment, return if not a kernel call vector

diff --git a/src/core/DynaRec_x64/recompiler.h b/src/core/DynaRec_x64/recompiler.h
@@ -36,13 +36,13 @@
 #include "spu/interface.h"
 #include "tracy/public/tracy/Tracy.hpp"
 
-#define HOST_REG_CACHE_OFFSET(x) ((uintptr_t)&m_hostRegisterCache[(x)] - (uintptr_t)this)
-#define GPR_OFFSET(x) ((uintptr_t)&m_regs.GPR.r[(x)] - (uintptr_t)this)
-#define COP0_OFFSET(x) ((uintptr_t)&m_regs.CP0.r[(x)] - (uintptr_t)this)
-#define PC_OFFSET ((uintptr_t)&m_regs.pc - (uintptr_t)this)
-#define LO_OFFSET ((uintptr_t)&m_regs.GPR.n.lo - (uintptr_t)this)
-#define HI_OFFSET ((uintptr_t)&m_regs.GPR.n.hi - (uintptr_t)this)
-#define CYCLE_OFFSET ((uintptr_t)&m_regs.cycle - (uintptr_t)this)
+#define HOST_REG_CACHE_OFFSET(x) ((uintptr_t) & m_hostRegisterCache[(x)] - (uintptr_t)this)
+#define GPR_OFFSET(x) ((uintptr_t) & m_regs.GPR.r[(x)] - (uintptr_t)this)
+#define COP0_OFFSET(x) ((uintptr_t) & m_regs.CP0.r[(x)] - (uintptr_t)this)
+#define PC_OFFSET ((uintptr_t) & m_regs.pc - (uintptr_t)this)
+#define LO_OFFSET ((uintptr_t) & m_regs.GPR.n.lo - (uintptr_t)this)
+#define HI_OFFSET ((uintptr_t) & m_regs.GPR.n.hi - (uintptr_t)this)
+#define CYCLE_OFFSET ((uintptr_t) & m_regs.cycle - (uintptr_t)this)
 
 #undef _PC_
 #undef _Op_

diff --git a/src/core/DynaRec_x64/symbols.cc b/src/core/DynaRec_x64/symbols.cc
@@ -85,7 +85,7 @@ void DynaRecCPU::makeSymbols() {
         REGISTER_VARIABLE(m_regs.CP2C.r[i], COP2_controlRegs[i], 4);
     }
 
-    REGISTER_VARIABLE(m_regs.cycle, "m_cycles", 4);
+    REGISTER_VARIABLE(m_regs.cycle, "m_cycles", 8);
     REGISTER_VARIABLE(m_regs.pc, "m_pc", 4);
 
     for (int i = 0; i < 16; i++) {  // Register host register cache

diff --git a/src/core/cdrom.cc b/src/core/cdrom.cc
@@ -580,7 +580,9 @@ class CDRomImpl : public PCSX::CDRom {
 
         if (m_irqRepeated) {
             m_irqRepeated = 0;
-            if (m_eCycle > PCSX::g_emulator->m_cpu->m_regs.cycle) {
+            auto &regs = PCSX::g_emulator->m_cpu->m_regs;
+            auto diff = regs.intTargets[PCSX::PSXINT_CDR] - regs.cycle;
+            if (m_eCycle > diff) {
                 scheduleCDIRQ(m_eCycle);
                 goto finish;
             }

diff --git a/src/core/decode_xa.cc b/src/core/decode_xa.cc
@@ -23,7 +23,7 @@
 
 #include "core/decode_xa.h"
 
-//#define FIXED
+// #define FIXED
 
 #define NOT(_X_) (!(_X_))
 #define XACLAMP(_X_, _MI_, _MA_)    \
@@ -274,7 +274,7 @@ typedef struct {
 #define SUB_SUB_VIDEO (1 << 1)    // contains video
 #define SUB_SUB_EOR (1 << 0)      // end of record
 
-#define AUDIO_CODING_GET_STEREO(_X_) ((_X_)&3)
+#define AUDIO_CODING_GET_STEREO(_X_) ((_X_) & 3)
 #define AUDIO_CODING_GET_FREQ(_X_) (((_X_) >> 2) & 3)
 #define AUDIO_CODING_GET_BPS(_X_) (((_X_) >> 4) & 3)
 #define AUDIO_CODING_GET_EMPHASIS(_X_) (((_X_) >> 6) & 1)

diff --git a/src/core/disr3000a.cc b/src/core/disr3000a.cc
@@ -68,7 +68,7 @@ const char *PCSX::Disasm::s_disRNameCP0[] = {
 
 #define declare(n) \
     void PCSX::Disasm::n(uint32_t code, uint32_t nextCode, uint32_t pc, bool *skipNext, bool *delaySlotNext)
-#define _Funct_ ((code)&0x3F)       // The funct part of the instruction register
+#define _Funct_ ((code) & 0x3F)     // The funct part of the instruction register
 #define _Rd_ ((code >> 11) & 0x1F)  // The rd part of the instruction register
 #define _Rt_ ((code >> 16) & 0x1F)  // The rt part of the instruction register
 #define _Rs_ ((code >> 21) & 0x1F)  // The rs part of the instruction register

diff --git a/src/core/gpu.cc b/src/core/gpu.cc
@@ -533,7 +533,7 @@ void PCSX::GPU::dma(uint32_t madr, uint32_t bcr, uint32_t chcr) {  // GPU
             PSXDMA_LOG("*** DMA 2 - GPU dma chain *** %8.8lx addr = %lx size = %lx\n", chcr, madr, bcr);
 
             size = gpuDmaChainSize(madr);
-            chainedDMAWrite((uint32_t *)PCSX::g_emulator->m_mem->m_wram, madr & 0x1fffff);
+            chainedDMAWrite((uint32_t *)PCSX::g_emulator->m_mem->m_wram, madr);
 
             // Tekken 3 = use 1.0 only (not 1.5x)
 
@@ -685,10 +685,8 @@ void PCSX::GPU::chainedDMAWrite(const uint32_t *memory, uint32_t hwAddr) {
 
     s_usedAddr[0] = s_usedAddr[1] = s_usedAddr[2] = 0xffffff;
 
-    const bool ramExpansion = PCSX::g_emulator->settings.get<PCSX::Emulator::Setting8MB>();
-
     do {
-        addr &= ramExpansion ? 0x7ffffc : 0x1ffffc;
+        addr &= g_emulator->getRamMask<4>();
 
         if (DMACommandCounter++ > 2000000) break;
         if (CheckForEndlessLoop(addr)) break;

diff --git a/src/core/gte.h b/src/core/gte.h
@@ -27,7 +27,7 @@
 #undef NCCS
 
 #define gteoB (PCSX::g_emulator->m_cpu->m_regs.GPR.r[_Rs_] + _Imm_)
-#define gteop(instruction) ((instruction)&0x1ffffff)
+#define gteop(instruction) ((instruction) & 0x1ffffff)
 
 namespace PCSX {
 

diff --git a/src/core/logger.h b/src/core/logger.h
@@ -54,7 +54,7 @@ enum class LogClass : unsigned {
 template <LogClass logClass, bool enabled>
 struct Logger {
     template <typename... Args>
-    static void Log(const char *format, const Args &... args) {
+    static void Log(const char *format, const Args &...args) {
         if (!enabled) return;
         std::string s = fmt::sprintf(format, args...);
         g_system->log(logClass, std::move(s));

diff --git a/src/core/mdec.cc b/src/core/mdec.cc
@@ -248,7 +248,7 @@ unsigned short *PCSX::MDEC::rl2blk(int *blk, unsigned short *mdec_rl) {
 // B = 1.000 * (Y) + 1.765 * (Cb - 128)
 #define MULR(a) ((1434 * (a)))
 #define MULB(a) ((1807 * (a)))
-#define MULG2(a, b) ((-351 * (a)-728 * (b)))
+#define MULG2(a, b) ((-351 * (a) - 728 * (b)))
 #define MULY(a) ((a) << 10)
 
 #define MAKERGB15(r, g, b, a) (SWAP_LE16(a | ((b) << 10) | ((g) << 5) | (r)))

diff --git a/src/core/patchmanager.cc b/src/core/patchmanager.cc
@@ -18,8 +18,9 @@
  ***************************************************************************/
 
 #include "core/patchmanager.h"
-#include "core/psxmem.h"
+
 #include "core/psxemulator.h"
+#include "core/psxmem.h"
 #include "core/r3000a.h"
 
 int PCSX::PatchManager::registerPatch(uint32_t address, Patch::Type type) {
@@ -71,13 +72,14 @@ void PCSX::PatchManager::undoPatch(Patch& patch) {
     patch.active = false;
 }
 
-PCSX::PatchManager::Patch::Type PCSX::PatchManager::findPatch(uint32_t address) const {
+int PCSX::PatchManager::findPatch(uint32_t address) const {
+    int idx = 0;
     for (const Patch& patch : m_patches) {
         if (patch.addr == address) {
-            return patch.type;
+            return idx;
         }
     }
-    return PCSX::PatchManager::Patch::Type::None;
+    return -1;
 }
 
 void PCSX::PatchManager::deletePatch(uint32_t index) {

diff --git a/src/core/patchmanager.h b/src/core/patchmanager.h
@@ -20,6 +20,7 @@
 #pragma once
 
 #include <stdint.h>
+
 #include <vector>
 
 namespace PCSX {
@@ -47,7 +48,7 @@ class PatchManager {
     Patch& getPatch(int index) { return m_patches[index]; }
 
     int registerPatch(uint32_t address, Patch::Type type);
-    PatchManager::Patch::Type findPatch(uint32_t address) const;
+    int findPatch(uint32_t address) const;
     void deletePatch(uint32_t index);
     void deleteAllPatches();
     void deactivateAll();

diff --git a/src/core/pcsxffi.lua b/src/core/pcsxffi.lua
@@ -50,6 +50,7 @@ typedef struct {
 enum BreakpointType { Exec, Read, Write };
 typedef struct { uint8_t opaque[?]; } Breakpoint;
 
+uint64_t getCPUCycles();
 uint8_t* getMemPtr();
 uint8_t* getParPtr();
 uint8_t* getRomPtr();
@@ -172,6 +173,7 @@ local function jumpToMemory(address, width)
 end
 
 PCSX = {
+    getCPUCycles = function() return C.getCPUCycles() end,
     getMemPtr = function() return C.getMemPtr() end,
     getParPtr = function() return C.getParPtr() end,
     getRomPtr = function() return C.getRomPtr() end,

diff --git a/src/core/pcsxlua.cc b/src/core/pcsxlua.cc
@@ -34,6 +34,7 @@ struct LuaBreakpoint {
     PCSX::Debug::BreakpointUserListType wrapper;
 };
 
+uint64_t getCPUCycles() { return PCSX::g_emulator->m_cpu->m_regs.cycle;  }
 void* getMemPtr() { return PCSX::g_emulator->m_mem->m_wram; }
 void* getParPtr() { return PCSX::g_emulator->m_mem->m_exp1; }
 void* getRomPtr() { return PCSX::g_emulator->m_mem->m_bios; }
@@ -137,6 +138,7 @@ static void registerAllSymbols(PCSX::Lua L) {
     L.getfieldtable("_CLIBS", LUA_REGISTRYINDEX);
     L.push("PCSX");
     L.newtable();
+    REGISTER(L, getCPUCycles);
     REGISTER(L, getMemPtr);
     REGISTER(L, getParPtr);
     REGISTER(L, getRomPtr);

diff --git a/src/core/pgxp_cpu.cc b/src/core/pgxp_cpu.cc
@@ -15,7 +15,7 @@ PGXP_value* const g_CP0_reg = s_CP0_reg_mem;
 
 // Instruction register decoding
 #define op(_instr) (_instr >> 26)           // The op part of the instruction register
-#define func(_instr) ((_instr)&0x3F)        // The funct part of the instruction register
+#define func(_instr) ((_instr) & 0x3F)      // The funct part of the instruction register
 #define sa(_instr) ((_instr >> 6) & 0x1F)   // The sa part of the instruction register
 #define rd(_instr) ((_instr >> 11) & 0x1F)  // The rd part of the instruction register
 #define rt(_instr) ((_instr >> 16) & 0x1F)  // The rt part of the instruction register
@@ -427,9 +427,9 @@ void PGXP_CPU_SLT(uint32_t instr, uint32_t rdVal, uint32_t rsVal, uint32_t rtVal
     ret.y = 0.f;
     ret.compFlags[1] = VALID;
 
-    ret.x = (g_CPU_reg[rs(instr)].y < g_CPU_reg[rt(instr)].y)
-                ? 1.f
-                : (f16Unsign(g_CPU_reg[rs(instr)].x) < f16Unsign(g_CPU_reg[rt(instr)].x)) ? 1.f : 0.f;
+    ret.x = (g_CPU_reg[rs(instr)].y < g_CPU_reg[rt(instr)].y)                         ? 1.f
+            : (f16Unsign(g_CPU_reg[rs(instr)].x) < f16Unsign(g_CPU_reg[rt(instr)].x)) ? 1.f
+                                                                                      : 0.f;
 
     ret.value = rdVal;
     g_CPU_reg[rd(instr)] = ret;
@@ -452,9 +452,9 @@ void PGXP_CPU_SLTU(uint32_t instr, uint32_t rdVal, uint32_t rsVal, uint32_t rtVa
     ret.y = 0.f;
     ret.compFlags[1] = VALID;
 
-    ret.x = (f16Unsign(g_CPU_reg[rs(instr)].y) < f16Unsign(g_CPU_reg[rt(instr)].y))
-                ? 1.f
-                : (f16Unsign(g_CPU_reg[rs(instr)].x) < f16Unsign(g_CPU_reg[rt(instr)].x)) ? 1.f : 0.f;
+    ret.x = (f16Unsign(g_CPU_reg[rs(instr)].y) < f16Unsign(g_CPU_reg[rt(instr)].y))   ? 1.f
+            : (f16Unsign(g_CPU_reg[rs(instr)].x) < f16Unsign(g_CPU_reg[rt(instr)].x)) ? 1.f
+                                                                                      : 0.f;
 
     ret.value = rdVal;
     g_CPU_reg[rd(instr)] = ret;

diff --git a/src/core/pgxp_debug.cc b/src/core/pgxp_debug.cc
@@ -9,7 +9,7 @@ unsigned int g_pgxp_debug = 0;
 
 // Instruction register decoding
 #define op(_instr) (_instr >> 26)           // The op part of the instruction register
-#define func(_instr) ((_instr)&0x3F)        // The funct part of the instruction register
+#define func(_instr) ((_instr) & 0x3F)      // The funct part of the instruction register
 #define sa(_instr) ((_instr >> 6) & 0x1F)   // The sa part of the instruction register
 #define rd(_instr) ((_instr >> 11) & 0x1F)  // The rd part of the instruction register
 #define rt(_instr) ((_instr >> 16) & 0x1F)  // The rt part of the instruction register

diff --git a/src/core/pgxp_debug.h b/src/core/pgxp_debug.h
@@ -30,10 +30,10 @@
 
 #include "psxemulator.h"
 
-//#define PGXP_CPU_DEBUG
-//#define PGXP_OUTPUT_ALL
-//#define PGXP_FORCE_INPUT_VALUES
-//#define PGXP_TEST_OUTPUT_VALUES
+// #define PGXP_CPU_DEBUG
+// #define PGXP_OUTPUT_ALL
+// #define PGXP_FORCE_INPUT_VALUES
+// #define PGXP_TEST_OUTPUT_VALUES
 
 #define PGXP_DEBUG_TOLERANCE 2.f
 

diff --git a/src/core/pgxp_gte.cc b/src/core/pgxp_gte.cc
@@ -57,7 +57,7 @@ void PGXP_InitGTE() {
 
 // Instruction register decoding
 #define op(_instr) (_instr >> 26)           // The op part of the instruction register
-#define func(_instr) ((_instr)&0x3F)        // The funct part of the instruction register
+#define func(_instr) ((_instr) & 0x3F)      // The funct part of the instruction register
 #define sa(_instr) ((_instr >> 6) & 0x1F)   // The sa part of the instruction register
 #define rd(_instr) ((_instr >> 11) & 0x1F)  // The rd part of the instruction register
 #define rt(_instr) ((_instr >> 16) & 0x1F)  // The rt part of the instruction register

diff --git a/src/core/pgxp_value.h b/src/core/pgxp_value.h
@@ -93,7 +93,7 @@ typedef enum { VALID_HALF = (1 << 0) } PGXP_half_flags;
 
 // typedef enum
 //{
-//#define NONE 0
+// #define NONE 0
 #define ALL 0xFFFFFFFF
 #define VALID 1
 #define VALID_0 (VALID << 0)