Fix matching issues in timer

peripherals/timer/timer_13_16_comcen.yaml

@@ -2,7 +2,7 @@
 #
 # SPDX-License-Identifier: MIT OR Apache-2.0
 
-"TIMER1[3-6]":
-  CHCTL[01]_Output:
+"TIMER1[3456]":
+  "CHCTL[01]_Output":
     "CH?COMCEN":
       _derivedFrom: "TIMER0.CHCTL0_Output.CH0COMCEN.CH0COMCEN"

peripherals/timer/timer_16bit_f2.yaml

@@ -9,6 +9,6 @@
   CAR:
     CAR: [0, 0xFFFF]
 
-"TIMER[0-4],TIMER[7-9],TIMER1[0-3]":
+"TIMER[01234789],TIMER1[0123]":
   "CH?CV":
     "CH?VAL": [0, 0xFFFF]

peripherals/timer/timer_advanced_f2.yaml

@@ -6,9 +6,9 @@
 
 TIMER0:
   CTL1:
-    "ISO[2-3]":
+    "ISO[23]":
       _derivedFrom: "ISO0"
-    "ISO[1-2]N":
+    "ISO[12]N":
       _derivedFrom: "ISO0N"
   DMAINTEN:
     CMTDEN:

peripherals/timer/timer_basic.yaml

@@ -4,7 +4,7 @@
 
 # Common features found on all timers.
 
-TIMER0:
+"TIMER*":
   CTL0:
     ARSE:
       Disabled: [0, "The shadow register for CAR is disabled"]
@@ -34,27 +34,5 @@ TIMER0:
   SWEVG:
     UPG:
       Update: [1, "Re-initializes the timer counter and generates an update of the registers."]
-
-"TIMER[1-9],TIMER1[0-9]":
-  CTL0:
-    ARSE:
-      _derivedFrom: "TIMER0.CTL0.ARSE.ARSE"
-    UPS:
-      _derivedFrom: "TIMER0.CTL0.UPS.UPS"
-    UPDIS:
-      _derivedFrom: "TIMER0.CTL0.UPDIS.UPDIS"
-    CEN:
-      _derivedFrom: "TIMER0.CTL0.CEN.CEN"
-  DMAINTEN:
-    UPIE:
-      _derivedFrom: "TIMER0.DMAINTEN.UPIE.UPIE"
-  INTF:
-    UPIF:
-      _derivedFrom: "TIMER0.INTF.UPIF.UPIF"
-  SWEVG:
-    UPG:
-      _derivedFrom: "TIMER0.SWEVG.UPG.UPG"
-
-"TIMER*":
   PSC:
     PSC: [0, 0xFFFF]

peripherals/timer/timer_dma_f2.yaml

@@ -3,7 +3,7 @@
 # SPDX-License-Identifier: MIT OR Apache-2.0
 
 # TIMER8-13 doesn't have single pulse mode or DMA.
-"TIMER[0-7]":
+"TIMER[01234567]":
   CTL0:
     SPM:
       Disabled: [0, "Counter is not stopped at update event"]
@@ -14,7 +14,7 @@
       Enabled: [1, "Update DMA request enabled"]
 
 # TIMER5/6 doesn't have DMA configuration registers or capture/compare.
-"TIMER[0-4],TIMER7":
+"TIMER[012347]":
   CTL1:
     DMAS:
       OnCompare: [0, "CCx DMA request sent when CCx event occurs"]

peripherals/timer/timer_general.yaml

@@ -5,40 +5,31 @@
 # TIMER5 is a basic timer, all the others are general or advanced, and so have compare mode (among
 # other things).
 
-# Use the same types for all timers, by deriving from one.
-TIMER0:
+"TIMER[01234]":
   CTL0:
     CKDIV:
       Div1: [0, "t_DTS = t_CK_INT"]
       Div2: [1, "t_DTS = 2 × t_CK_INT"]
       Div4: [2, "t_DTS = 4 × t_CK_INT"]
   DMAINTEN:
-    CH0IE:
+    "CH?IE":
       Disabled: [0, "Capture/compare interrupt disabled"]
       Enabled: [1, "Capture/compare interrupt enabled"]
-    "CH[1-3]IE":
-      _derivedFrom: "CH0IE"
   INTF:
-    CH0OF:
+    "CH?OF":
       Clear: [0, "No over capture occurred"]
       OverCapture: [1, "A capture event occured while CHnIF was already set"]
-    "CH[1-3]OF":
-      _derivedFrom: "CH0OF"
-    CH0IF:
+    "CH?IF":
       Clear: [0, "No capture or compare interrupt occurred"]
       CaptureCompare: [1, "A capture or compare event occurred"]
-    "CH[1-3]IF":
-      _derivedFrom: "CH0IF"
   SWEVG:
-    CH0G:
+    "CH?G":
       CaptureCompare: [1, "Generate a capture or compare event"]
-    "CH[1-3]G":
-      _derivedFrom: "CH0G"
-  CHCTL0_Output:
-    CH0COMCEN:
+  "CHCTL?_Output":
+    "CH?COMCEN":
       Disabled: [0, "Output compare clear disabled"]
       Enabled: [1, "Output compare clear enabled"]
-    CH0COMCTL:
+    "CH?COMCTL":
       Frozen:
         [
           0,
@@ -63,7 +54,7 @@ TIMER0:
           "In upcounting, channel is active as long as CNT<CHyCV else inactive. In downcounting, channel is inactive as long as CNT>CHyCV else active",
         ]
       PwmMode1: [7, "Inversely to PwmMode0"]
-    CH0COMSEN:
+    "CH?COMSEN":
       Disabled:
         [
           0,
@@ -74,27 +65,16 @@ TIMER0:
           1,
           "Preload register on CHyCV enabled. Preload value is loaded into active register on each update event",
         ]
-    CH0COMFEN:
+    "CH?COMFEN":
       Slow: [0, "The minimum delay from an edge is 5 clock cycles"]
       Fast: [1, "The minimum delay from an edge is 3 clock cycles"]
-    CH0MS:
+    "CH?MS":
       Output: [0, "Channel is configured as output"]
       CI0: [1, "Channel is configured as input, ISx is connected to CI0FE0"]
       CI1: [2, "Channel is configured as input, ISx is connected to CI1FE0"]
       ITS: [3, "Channel is configured as input, ISx is connected to ITS"]
-  CHCTL[01]_Output:
-    "CH[1-3]COMCEN":
-      _derivedFrom: "CHCTL0_Output.CH0COMCEN.CH0COMCEN"
-    "CH[1-3]COMCTL":
-      _derivedFrom: "CHCTL0_Output.CH0COMCTL.CH0COMCTL"
-    "CH[1-3]COMSEN":
-      _derivedFrom: "CHCTL0_Output.CH0COMSEN.CH0COMSEN"
-    "CH[1-3]COMFEN":
-      _derivedFrom: "CHCTL0_Output.CH0COMFEN.CH0COMFEN"
-    "CH[1-3]MS":
-      _derivedFrom: "CHCTL0_Output.CH0MS.CH0MS"
-  CHCTL0_Input:
-    CH0CAPFLT:
+  "CHCTL?_Input":
+    "CH?CAPFLT":
       NoFilter: [0, "Filter disabled. fSAMP=fDTS, N=1"]
       TimerCk_N2: [1, "fSAMP=fTIMER_CK, N=2"]
       TimerCk_N4: [2, "fSAMP=fTIMER_CK, N=4"]
@@ -111,72 +91,20 @@ TIMER0:
       FDTS_Div32_N5: [13, "fSAMP=fDTS/32, N=5"]
       FDTS_Div32_N6: [14, "fSAMP=fDTS/32, N=6"]
       FDTS_Div32_N8: [15, "fSAMP=fDTS/32, N=8"]
-    CH0CAPPSC:
+    "CH?CAPPSC":
       Div1: [0, "Prescaler disabled, capture on every edge"]
       Div2: [1, "Capture every 2 edges"]
       Div4: [2, "Capture every 4 edges"]
       Div8: [3, "Capture every 8 edges"]
-    CH0MS:
+    "CH?MS":
       Output: [0, "Channel is configured as output"]
       CI0: [1, "Channel is configured as input, ISx is connected to CI0FEx"]
       CI1: [2, "Channel is configured as input, ISx is connected to CI1FEx"]
       ITS: [3, "Channel is configured as input, ISx is connected to ITS"]
-  "CHCTL[01]_Input":
-    "CH[1-3]CAPFLT":
-      _derivedFrom: "CHCTL0_Input.CH0CAPFLT.CH0CAPFLT"
-    "CH[1-3]CAPPSC":
-      _derivedFrom: "CHCTL0_Input.CH0CAPPSC.CH0CAPPSC"
-    "CH[1-3]MS":
-      _derivedFrom: "CHCTL0_Input.CH0MS.CH0MS"
   CHCTL2:
-    CH0P:
+    "CH*P":
       NotInverted: [0, "Active high"]
       Inverted: [1, "Active low"]
-    "CH[1-3]P,CH?NP":
-      _derivedFrom: "CH0P"
-    CH0EN:
+    "CH?EN":
       Disabled: [0, "Channel output is disabled"]
       Enabled: [1, "Channel output is enabled"]
-    "CH[1-3]EN":
-      _derivedFrom: "CH0EN"
-
-"TIMER[1-2],TIMER1[3-6]":
-  CTL0:
-    CKDIV:
-      _derivedFrom: "TIMER0.CTL0.CKDIV.CKDIV"
-  DMAINTEN:
-    "CH?IE":
-      _derivedFrom: "TIMER0.DMAINTEN.CH0IE.CH0IE"
-  INTF:
-    "CH?OF":
-      _derivedFrom: "TIMER0.INTF.CH0OF.CH0OF"
-    "CH?IF":
-      _derivedFrom: "TIMER0.INTF.CH0IF.CH0IF"
-  SWEVG:
-    "CH?G":
-      _derivedFrom: "TIMER0.SWEVG.CH0G.CH0G"
-  CHCTL[01]_Output:
-    "CH?COMCTL":
-      _derivedFrom: "TIMER0.CHCTL0_Output.CH0COMCTL.CH0COMCTL"
-    "CH?COMSEN":
-      _derivedFrom: "TIMER0.CHCTL0_Output.CH0COMSEN.CH0COMSEN"
-    "CH?COMFEN":
-      _derivedFrom: "TIMER0.CHCTL0_Output.CH0COMFEN.CH0COMFEN"
-    "CH?MS":
-      _derivedFrom: "TIMER0.CHCTL0_Output.CH0MS.CH0MS"
-  "CHCTL[01]_Input":
-    "CH?CAPFLT":
-      _derivedFrom: "TIMER0.CHCTL0_Input.CH0CAPFLT.CH0CAPFLT"
-    "CH?CAPPSC":
-      _derivedFrom: "TIMER0.CHCTL0_Input.CH0CAPPSC.CH0CAPPSC"
-    "CH?MS":
-      _derivedFrom: "TIMER0.CHCTL0_Input.CH0MS.CH0MS"
-  CHCTL2:
-    "CH?P,CH?NP":
-      _derivedFrom: "TIMER0.CHCTL2.CH0P.CH0P"
-    "CH?EN":
-      _derivedFrom: "TIMER0.CHCTL2.CH0EN.CH0EN"
-"TIMER[1-2]":
-  CHCTL[01]_Output:
-    "CH?COMCEN":
-      _derivedFrom: "TIMER0.CHCTL0_Output.CH0COMCEN.CH0COMCEN"

peripherals/timer/timer_interconnect.yaml

@@ -5,7 +5,7 @@
 # Interconnection and slave mode.
 # Timers 13-16 don't have interconnection.
 
-"TIMER[0-2],TIMER14":
+"TIMER[012],TIMER14":
   SMCFG:
     MSM:
       NoSync: [0, "No action"]
@@ -45,14 +45,14 @@ TIMER0:
       CompareO2C: [6, "O2CPRE signal is used as trigger output"]
       CompareO3C: [7, "O3CPRE signal is used as trigger output"]
 
-"TIMER[1-5],TIMER14":
+"TIMER[12345],TIMER14":
   CTL1:
     MMC:
       Reset: [0, "Use UPG bit from SWEVG register"]
       Enable: [1, "Use CEN bit from CTL0 register"]
       Update: [2, "Use the update event"]
 
-"TIMER[0-2]":
+"TIMER[012]":
   CTL1:
     TI0S:
       Normal: [0, "The CH0 pin input is selected as channel 0 trigger input"]

peripherals/timer/timer_interconnect_f2.yaml

@@ -5,7 +5,7 @@
 # Interconnection and slave mode.
 # Timers 13-16 don't have interconnection.
 
-"TIMER[0-2],TIMER14":
+"TIMER[012],TIMER14":
   SMCFG:
     MSM:
       NoSync: [0, "No action"]
@@ -45,14 +45,14 @@ TIMER0:
       CompareO2C: [6, "O2CPRE signal is used as trigger output"]
       CompareO3C: [7, "O3CPRE signal is used as trigger output"]
 
-"TIMER[1-5],TIMER14":
+"TIMER[12345],TIMER14":
   CTL1:
     MMC:
       Reset: [0, "Use UPG bit from SWEVG register"]
       Enable: [1, "Use CEN bit from CTL0 register"]
       Update: [2, "Use the update event"]
 
-"TIMER[0-2]":
+"TIMER[012]":
   CTL1:
     TI0S:
       Normal: [0, "The CH0 pin input is selected as channel 0 trigger input"]

peripherals/timer/timer_updown.yaml

@@ -2,7 +2,7 @@
 #
 # SPDX-License-Identifier: MIT OR Apache-2.0
 
-TIMER0:
+"TIMER[012]":
   CTL0:
     CAM:
       EdgeAligned: [0, "The counter counts up or down depending on the direction bit"]
@@ -24,10 +24,3 @@ TIMER0:
     DIR:
       Up: [0, "Counter used as upcounter"]
       Down: [1, "Counter used as downcounter"]
-
-"TIMER[1-2]":
-  CTL0:
-    CAM:
-      _derivedFrom: "TIMER0.CTL0.CAM.CAM"
-    DIR:
-      _derivedFrom: "TIMER0.CTL0.DIR.DIR"

peripherals/timer/timers_high.yaml

@@ -2,13 +2,13 @@
 #
 # SPDX-License-Identifier: MIT OR Apache-2.0
 
-"TIMER[0-2],TIMER1[3-6]":
+"TIMER[012],TIMER1[3456]":
   CFG:
     CHVSEL:
       Normal: [0, "Normal behaviour"]
       IgnoreSame: [1, "Duplicate writes to CHxVAL are ignored"]
 
-"TIMER0,TIMER1[4-6]":
+"TIMER0,TIMER1[456]":
   CFG:
     OUTSEL:
       Normal: [0, "Normal behaviour"]