Stop using APIs removed from chisel3 (#309)

* provide polyfill for chisel3.Driver and related APIs
* fix for remove io
* no more MultiIOModule

src/main/scala/chisel3/iotesters/ChiselMain.scala

@@ -82,13 +82,13 @@ object chiselMain {
         // Copy API files
         copyVerilatorHeaderFiles(context.targetDir.toString)
         // Generate Verilator
-        assert(chisel3.Driver.verilogToCpp(
+        assert(firrtl.util.BackendCompilationUtilities.verilogToCpp(
           dutName,
           dir,
           Seq(),
           new File(dir, s"$dutName-harness.cpp")).! == 0)
         // Compile Verilator
-        assert(chisel3.Driver.cppToExe(dutName, dir).! == 0)
+        assert(firrtl.util.BackendCompilationUtilities.cppToExe(dutName, dir).! == 0)
       case "vcs" | "glsim" =>
         // Copy API files
         copyVpiFiles(context.targetDir.toString)
@@ -107,33 +107,33 @@ object chiselMain {
       case x: IOException =>
         System.err.format("createFile error: %s%n", x)
     }
-    val circuit = chisel3.Driver.elaborate(dutGen)
-    val dut = getTopModule(circuit).asInstanceOf[T]
-    val nodes = getChiselNodes(circuit)
+    val cir = chisel3.stage.ChiselStage.elaborate(dutGen())
+    val dut = getTopModule(cir).asInstanceOf[T]
+    val nodes = getChiselNodes(cir)
     val dir = context.targetDir
-    val name = circuit.name
+    val name = cir.name
 
-    val chirrtl = firrtl.Parser.parse(chisel3.Driver.emit(circuit))
+    val fir = chisel3.stage.ChiselStage.convert(dutGen())
     val chirrtlFile = new File(dir, s"$name.ir")
     val verilogFile = new File(dir, s"$name.v")
     context.backendType match {
       case "firrtl" =>
         val writer = new FileWriter(chirrtlFile)
-        (new firrtl.LowFirrtlEmitter).emit(firrtl.CircuitState(chirrtl, firrtl.ChirrtlForm), writer)
+        (new firrtl.LowFirrtlEmitter).emit(firrtl.CircuitState(fir, firrtl.ChirrtlForm), writer)
         writer.close()
       case _ if context.isGenVerilog =>
         val annotations = Seq(firrtl.passes.memlib.InferReadWriteAnnotation)
         val writer = new FileWriter(verilogFile)
         val compileResult = (new firrtl.VerilogCompiler).compileAndEmit(
-          firrtl.CircuitState(chirrtl, firrtl.ChirrtlForm, annotations),
+          firrtl.CircuitState(fir, firrtl.ChirrtlForm, annotations),
           List(new firrtl.passes.memlib.InferReadWrite)
         )
         writer.write(compileResult.getEmittedCircuit.value)
         writer.close()
       case _ =>
     }
 
-    if (context.isGenHarness) genHarness(dut, nodes, chirrtl)
+    if (context.isGenHarness) genHarness(dut, nodes, fir)
 
     if (context.isCompiling) compile(name)
 

src/main/scala/chisel3/iotesters/ChiselSpec.scala

@@ -23,7 +23,7 @@ trait ChiselRunners extends Assertions {
   def assertTesterPasses(t: => BasicTester, additionalVResources: Seq[String] = Seq()): Unit = {
     assert(runTester(t, additionalVResources))
   }
-  def elaborate(t: => Module): Unit = chisel3.Driver.elaborate(() => t)
+  def elaborate(t: => Module): Unit = chisel3.stage.ChiselStage.elaborate(t)
 }
 
 /** Spec base class for BDD-style testers. */

src/main/scala/chisel3/iotesters/Driver.scala

@@ -2,9 +2,10 @@
 
 package chisel3.iotesters
 
-import chisel3._
+import chisel3.{ChiselExecutionFailure => _, ChiselExecutionResult => _, ChiselExecutionSuccess => _, _}
 import java.io.File
 
+import chisel3.iotesters.DriverCompatibility._
 import firrtl.annotations.Annotation
 import firrtl_interpreter._
 import logger.Logger
@@ -27,7 +28,7 @@ object Driver {
     * @param testerGen       A peek poke tester with tests for the dut
     * @return                Returns true if all tests in testerGen pass
     */
-  def execute[T <: MultiIOModule](
+  def execute[T <: Module](
                             dutGenerator: () => T,
                             optionsManager: TesterOptionsManager,
                             firrtlSourceOverride: Option[String] = None
@@ -93,7 +94,7 @@ object Driver {
     * @param testerGen  A peek-poke tester with test for the dey
     * @return           Returns true if all tests in testerGen pass
     */
-  def execute[T <: MultiIOModule](args: Array[String], dut: () => T)(
+  def execute[T <: Module](args: Array[String], dut: () => T)(
     testerGen: T => PeekPokeTester[T]
   ): Boolean = {
     val optionsManager = new TesterOptionsManager
@@ -125,7 +126,7 @@ object Driver {
     * @param optionsManager options
     * @return
     */
-  def executeFirrtlRepl[T <: MultiIOModule](
+  def executeFirrtlRepl[T <: Module](
                                       dutGenerator: () => T,
                                       optionsManager: ReplOptionsManager = new ReplOptionsManager): Boolean = {
 
@@ -142,7 +143,7 @@ object Driver {
     optionsManager.firrtlOptions = optionsManager.firrtlOptions.copy(compilerName = "low")
 
     Logger.makeScope(optionsManager) {
-      val chiselResult: ChiselExecutionResult = chisel3.Driver.execute(optionsManager, dutGenerator)
+      val chiselResult: ChiselExecutionResult = DriverCompatibility.execute(optionsManager, dutGenerator)
       chiselResult match {
         case ChiselExecutionSuccess(_, emitted, _) =>
           optionsManager.replConfig = optionsManager.replConfig.copy(firrtlSource = emitted)
@@ -171,7 +172,7 @@ object Driver {
     * @param args           options from the command line
     * @return
     */
-  def executeFirrtlRepl[T <: MultiIOModule](
+  def executeFirrtlRepl[T <: Module](
                                     args: Array[String],
                                       dutGenerator: () => T
                                       ): Boolean = {
@@ -225,7 +226,7 @@ object Driver {
     * @param testerGen   This is a test harness subclassing PeekPokeTester for dutGen,
     * @return            This will be true if all tests in the testerGen pass
     */
-  def apply[T <: MultiIOModule](
+  def apply[T <: Module](
       dutGen: () => T,
       backendType: String = "firrtl",
       verbose: Boolean = false,
@@ -243,9 +244,9 @@ object Driver {
     * Runs the ClassicTester using the verilator backend without doing Verilator compilation and returns a Boolean indicating success or failure
     * Requires the caller to supply path the already compile Verilator binary
     */
-  def run[T <: MultiIOModule](dutGen: () => T, cmd: Seq[String])
+  def run[T <: Module](dutGen: () => T, cmd: Seq[String])
                       (testerGen: T => PeekPokeTester[T]): Boolean = {
-    val circuit = chisel3.Driver.elaborate(dutGen)
+    val circuit = chisel3.stage.ChiselStage.elaborate(dutGen())
     val dut = getTopModule(circuit).asInstanceOf[T]
     backendVar.withValue(Some(new VerilatorBackend(dut, cmd))) {
       try {
@@ -268,11 +269,11 @@ object Driver {
     }
   }
 
-  def run[T <: MultiIOModule](dutGen: () => T, binary: String, args: String*)
+  def run[T <: Module](dutGen: () => T, binary: String, args: String*)
                       (testerGen: T => PeekPokeTester[T]): Boolean =
     run(dutGen, binary +: args.toSeq)(testerGen)
 
-  def run[T <: MultiIOModule](dutGen: () => T, binary: File, waveform: Option[File] = None)
+  def run[T <: Module](dutGen: () => T, binary: File, waveform: Option[File] = None)
                       (testerGen: T => PeekPokeTester[T]): Boolean = {
     val args = waveform match {
       case None => Nil