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Github: fix non zero return behavior in docker actions. Firmware: fix F6 build. #886

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merged 3 commits into from
Dec 9, 2021
Merged

Github: fix non zero return behavior in docker actions. Firmware: fix F6 build. #886

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75844ca
Github: treat non 0 exit code as fatal
skotopes Dec 8, 2021
e7a60cc
GitHub: inject missing -e flag to bash in docker
skotopes Dec 8, 2021
4eb3a11
Firmware: sync targets
skotopes Dec 8, 2021
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2 changes: 2 additions & 0 deletions .github/workflows/build.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -82,6 +82,7 @@ jobs:
uses: ./.github/actions/docker
with:
run: |
set -e
for TARGET in ${TARGETS}
do
make TARGET=${TARGET}
Expand All @@ -92,6 +93,7 @@ jobs:
uses: ./.github/actions/docker
with:
run: |
set -e
for TARGET in ${TARGETS}
do
mv dist/${TARGET}/* artifacts/
Expand Down
1 change: 1 addition & 0 deletions firmware/targets/f6/ble-glue/serial_service.h
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Expand Up @@ -4,6 +4,7 @@
#include <stdbool.h>

#define SERIAL_SVC_DATA_LEN_MAX (486)
#define SERIAL_SVC_CHAR_VALUE_LEN_MAX (243)

#ifdef __cplusplus
extern "C" {
Expand Down
22 changes: 9 additions & 13 deletions firmware/targets/f6/furi-hal/furi-hal-subghz.c
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Expand Up @@ -296,9 +296,9 @@ static const uint8_t furi_hal_subghz_preset_gfsk_9_99kb_async_regs[][2] = {
{CC1101_IOCFG0, 0x06}, //GDO0 Output Pin Configuration
{CC1101_FIFOTHR, 0x47}, //RX FIFO and TX FIFO Thresholds

//1 : CRC calculation in TX and CRC check in RX enabled,
//1 : CRC calculation in TX and CRC check in RX enabled,
//1 : Variable packet length mode. Packet length configured by the first byte after sync word
{CC1101_PKTCTRL0, 0x05},
{CC1101_PKTCTRL0,0x05},

{CC1101_FSCTRL1, 0x06}, //Frequency Synthesizer Control

Expand All @@ -314,8 +314,8 @@ static const uint8_t furi_hal_subghz_preset_gfsk_9_99kb_async_regs[][2] = {
{CC1101_DEVIATN, 0x34}, //Deviation = 19.042969
{CC1101_MCSM0, 0x18}, //Main Radio Control State Machine Configuration
{CC1101_FOCCFG, 0x16}, //Frequency Offset Compensation Configuration

{CC1101_AGCCTRL2, 0x43}, //AGC Control
{CC1101_AGCCTRL2, 0x43 }, //AGC Control
{CC1101_AGCCTRL1, 0x40},
{CC1101_AGCCTRL0, 0x91},

Expand Down Expand Up @@ -392,8 +392,7 @@ void furi_hal_subghz_init() {
;

// GD0 high
cc1101_write_reg(
&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG0, CC1101IocfgHW | CC1101_IOCFG_INV);
cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG0, CC1101IocfgHW | CC1101_IOCFG_INV);
while(hal_gpio_read(&gpio_cc1101_g0) != true)
;

Expand Down Expand Up @@ -454,7 +453,7 @@ void furi_hal_subghz_load_preset(FuriHalSubGhzPreset preset) {
} else if(preset == FuriHalSubGhzPresetGFSK9_99KbAsync) {
furi_hal_subghz_load_registers(furi_hal_subghz_preset_gfsk_9_99kb_async_regs);
furi_hal_subghz_load_patable(furi_hal_subghz_preset_gfsk_async_patable);
} else {
} else{
furi_crash(NULL);
}
}
Expand Down Expand Up @@ -499,8 +498,7 @@ void furi_hal_subghz_flush_tx() {
bool furi_hal_subghz_rx_pipe_not_empty() {
CC1101RxBytes status[1];
furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
cc1101_read_reg(
&furi_hal_spi_bus_handle_subghz, (CC1101_STATUS_RXBYTES) | CC1101_BURST, (uint8_t*)status);
cc1101_read_reg(&furi_hal_spi_bus_handle_subghz, (CC1101_STATUS_RXBYTES) | CC1101_BURST, (uint8_t*)status);
furi_hal_spi_release(&furi_hal_spi_bus_handle_subghz);
// TODO: you can add a buffer overflow flag if needed
if(status->NUM_RXBYTES > 0) {
Expand Down Expand Up @@ -674,15 +672,13 @@ void furi_hal_subghz_set_path(FuriHalSubGhzPath path) {
furi_hal_spi_acquire(&furi_hal_spi_bus_handle_subghz);
if(path == FuriHalSubGhzPath433) {
hal_gpio_write(&gpio_rf_sw_0, 0);
cc1101_write_reg(
&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
} else if(path == FuriHalSubGhzPath315) {
hal_gpio_write(&gpio_rf_sw_0, 1);
cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW);
} else if(path == FuriHalSubGhzPath868) {
hal_gpio_write(&gpio_rf_sw_0, 1);
cc1101_write_reg(
&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW | CC1101_IOCFG_INV);
} else if(path == FuriHalSubGhzPathIsolate) {
hal_gpio_write(&gpio_rf_sw_0, 0);
cc1101_write_reg(&furi_hal_spi_bus_handle_subghz, CC1101_IOCFG2, CC1101IocfgHW);
Expand Down
2 changes: 1 addition & 1 deletion firmware/targets/f6/furi-hal/furi-hal-uart.h
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Expand Up @@ -74,4 +74,4 @@ void furi_hal_uart_set_irq_cb(

#ifdef __cplusplus
}
#endif
#endif