Vitis Accelerator IP Flow

hls4ml/backends/__init__.py

@@ -2,17 +2,25 @@
 from hls4ml.backends.fpga.fpga_backend import FPGABackend  # noqa: F401
 from hls4ml.backends.quartus.quartus_backend import QuartusBackend
 from hls4ml.backends.symbolic.symbolic_backend import SymbolicExpressionBackend
+from hls4ml.backends.vitis_accelerator_ip_flow.vitis_accelerator_ip_flow_config import (  # noqa: F401
+    VitisAcceleratorIPFlowConfig,
+)
 from hls4ml.backends.vivado.vivado_backend import VivadoBackend
 from hls4ml.backends.vivado_accelerator.vivado_accelerator_backend import VivadoAcceleratorBackend
 from hls4ml.backends.vivado_accelerator.vivado_accelerator_config import VivadoAcceleratorConfig  # noqa: F401
 
+from hls4ml.backends.vitis_accelerator_ip_flow.vitis_accelerator_ip_flow_backend import (  # isort: skip
+    VitisAcceleratorIPFlowBackend,
+)
+
 from hls4ml.backends.catapult.catapult_backend import CatapultBackend  # isort: skip
 
 from hls4ml.backends.vitis.vitis_backend import VitisBackend  # isort: skip
 
 register_backend('Vivado', VivadoBackend)
 register_backend('VivadoAccelerator', VivadoAcceleratorBackend)
 register_backend('Vitis', VitisBackend)
+register_backend('VitisAcceleratorIPFlow', VitisAcceleratorIPFlowBackend)
 register_backend('Quartus', QuartusBackend)
 register_backend('Catapult', CatapultBackend)
 register_backend('SymbolicExpression', SymbolicExpressionBackend)

hls4ml/backends/vitis_accelerator_ip_flow/supported_boards.json

@@ -0,0 +1,42 @@
+{
+  "pynq-z2": {
+    "part": "xc7z020clg400-1",
+    "tcl_scripts": {"axi_lite": "axi_lite_design.tcl", "axi_stream":  "axi_stream_design.tcl"},
+    "python_drivers": {"axi_stream":  "axi_stream_driver.py"},
+    "c_drivers": {}
+  },
+  "zcu102": {
+    "part": "xczu9eg-ffvb1156-2-e",
+    "tcl_scripts": { "axi_stream": "axi_stream_design.tcl"},
+    "python_drivers": {"axi_stream":  "axi_stream_driver.py"},
+    "c_drivers": {}
+  },
+  "alveo-u50": {
+    "part": "xcu50-fsvh2104-2-e",
+    "tcl_scripts": {"axi_stream": "axi_stream_design.tcl"},
+    "python_drivers": {"axi_stream": "axi_stream_driver.py"},
+    "krnl_rtl_srcs": {"axi_stream":  "krnl_rtl_src"},
+    "c_drivers": {}
+  },
+  "alveo-u250": {
+    "part": "xcu250-figd2104-2L-e",
+    "tcl_scripts": {"axi_stream": "axi_stream_design.tcl"},
+    "python_drivers": {"axi_stream": "axi_stream_driver.py"},
+    "krnl_rtl_srcs": {"axi_stream":  "krnl_rtl_src"},
+    "c_drivers": {}
+  },
+  "alveo-u200": {
+    "part": "xcu200-fsgd2104-2-e",
+    "tcl_scripts": {"axi_stream": "axi_stream_design.tcl"},
+    "python_drivers": {"axi_stream": "axi_stream_driver.py"},
+    "krnl_rtl_srcs": {"axi_stream":  "krnl_rtl_src"},
+    "c_drivers": {}
+  },
+  "alveo-u280": {
+    "part": "xcu280-fsvh2892-2L-e",
+    "tcl_scripts": {"axi_stream": "axi_stream_design.tcl"},
+    "python_drivers": {"axi_stream": "axi_stream_driver.py"},
+    "krnl_rtl_srcs": {"axi_stream":  "krnl_rtl_src"},
+    "c_drivers": {}
+  }
+}

hls4ml/backends/vitis_accelerator_ip_flow/vitis_accelerator_ip_flow_backend.py

@@ -0,0 +1,122 @@
+import os
+
+from hls4ml.backends import VitisBackend, VivadoBackend
+from hls4ml.model.flow import register_flow
+from hls4ml.report import parse_vivado_report
+
+
+class VitisAcceleratorIPFlowBackend(VitisBackend):
+    def __init__(self):
+        super(VivadoBackend, self).__init__(name='VitisAcceleratorIPFlow')
+        self._register_layer_attributes()
+        self._register_flows()
+
+    def build(
+        self,
+        model,
+        reset=False,
+        csim=True,
+        synth=True,
+        cosim=False,
+        validation=False,
+        export=False,
+        vsynth=False,
+        # fifo_opt=False,
+        bitfile=False,
+    ):
+        # run the VitisBackend build
+        super().build(
+            model,
+            reset=reset,
+            csim=csim,
+            synth=synth,
+            cosim=cosim,
+            validation=validation,
+            export=export,
+            vsynth=vsynth,
+            # fifo_opt=fifo_opt,
+        )
+        # Get Config to view Board and Platform
+        # from hls4ml.backends import VitisAcceleratorIPFlowConfig
+
+        # vitis_accelerator_ip_flow_config = VitisAcceleratorIPFlowConfig(
+        #     model.config, model.get_input_variables(), model.get_output_variables()
+        # )
+        # now make a bitfile
+        if bitfile:
+            curr_dir = os.getcwd()
+            os.chdir(model.config.get_output_dir())
+            try:
+                os.system('vivado -mode batch -source design.tcl')  # check if this is accepted as a command
+            except Exception:
+                print("Something went wrong, check the Vivado logs")
+            os.chdir(curr_dir)
+
+        return parse_vivado_report(model.config.get_output_dir())
+
+    def create_initial_config(
+        self,
+        board='pynq-z2',
+        part=None,
+        clock_period=5,
+        clock_uncertainty='12.5%',
+        io_type='io_parallel',
+        interface='axi_stream',
+        driver='python',
+        input_type='float',
+        output_type='float',
+        platform='xilinx_u250_xdma_201830_2',
+    ):
+        '''
+        Create initial accelerator config with default parameters
+
+        Args:
+            board: one of the keys defined in supported_boards.json
+            clock_period: clock period passed to hls project
+            io_type: io_parallel or io_stream
+            interface: `axi_stream`: generate hardware designs and drivers which exploit axi stream channels.
+                       `axi_master`: generate hardware designs and drivers which exploit axi master channels.
+                       `axi_lite` : generate hardware designs and drivers which exploit axi lite channels. (Don't use it
+                       to exchange large amount of data)
+            driver: `python`: generates the python driver to use the accelerator in the PYNQ stack.
+                    `c`: generates the c driver to use the accelerator bare-metal.
+            input_type: the wrapper input precision. Can be `float` or an `ap_type`. Note: VivadoAcceleratorBackend
+                             will round the number of bits used to the next power-of-2 value.
+            output_type: the wrapper output precision. Can be `float` or an `ap_type`. Note:
+                              VivadoAcceleratorBackend will round the number of bits used to the next power-of-2 value.
+            platform: development target platform
+
+        Returns:
+            populated config
+        '''
+        board = board if board is not None else 'pynq-z2'
+        config = super().create_initial_config(part, clock_period, clock_uncertainty, io_type)
+        config['AcceleratorConfig'] = {}
+        config['AcceleratorConfig']['Board'] = board
+        config['AcceleratorConfig']['Interface'] = interface  # axi_stream, axi_master, axi_lite
+        config['AcceleratorConfig']['Driver'] = driver
+        config['AcceleratorConfig']['Precision'] = {}
+        config['AcceleratorConfig']['Precision']['Input'] = {}
+        config['AcceleratorConfig']['Precision']['Output'] = {}
+        config['AcceleratorConfig']['Precision']['Input'] = input_type  # float, double or ap_fixed<a,b>
+        config['AcceleratorConfig']['Precision']['Output'] = output_type  # float, double or ap_fixed<a,b>
+        # if board.startswith('alveo'):
+        #     config['AcceleratorConfig']['Platform'] = platform
+
+        return config
+
+    def get_default_flow(self):
+        return self._default_flow
+
+    def get_writer_flow(self):
+        return self._writer_flow
+
+    def _register_flows(self):
+        vivado_ip = 'vivado:ip'
+        writer_passes = ['make_stamp', 'vitisacceleratoripflow:write_hls']
+        self._writer_flow = register_flow('write', writer_passes, requires=[vivado_ip], backend=self.name)
+        self._default_flow = vivado_ip
+
+        # fifo_depth_opt_passes = ['vivadoaccelerator:fifo_depth_optimization'] + writer_passes
+
+        # register_flow('fifo_depth_optimization', fifo_depth_opt_passes, requires=[vivado_ip], backend=self.name)

hls4ml/backends/vitis_accelerator_ip_flow/vitis_accelerator_ip_flow_config.py

@@ -0,0 +1,169 @@
+import json
+import os
+
+import numpy as np
+
+from hls4ml.model.layers import FixedPrecisionType, IntegerPrecisionType
+
+
+class VitisAcceleratorIPFlowConfig:
+    def __init__(self, config, model_inputs, model_outputs):
+        self.config = config.config
+        self.board = self.config.get('AcceleratorConfig', {}).get('Board', 'pynq-z2')
+        self.supported_boards = json.load(open(os.path.dirname(__file__) + '/supported_boards.json'))
+        if self.board in self.supported_boards.keys():
+            board_info = self.supported_boards[self.board]
+            self.part = board_info['part']
+        else:
+            raise Exception('The board does not appear in supported_boards.json file')
+
+        if self.config.get('Part') is not None:
+            if self.config.get('Part') != self.part:
+                print(
+                    'WARNING: You set a Part that does not correspond to the Board you specified. The correct '
+                    'Part is now set.'
+                )
+                self.config['Part'] = self.part
+        accel_config = self.config.get('AcceleratorConfig', None)
+        if accel_config is not None:
+            prec = accel_config.get('Precision')
+            if prec is None:
+                raise Exception('Precision must be provided in the AcceleratorConfig')
+            else:
+                if prec.get('Input') is None or prec.get('Output') is None:
+                    raise Exception('Input and Output fields must be provided in the AcceleratorConfig->Precision')
+        else:
+            accel_config = {
+                'Precision': {'Input': 'float', 'Output': 'float'},
+                'Driver': 'python',
+                'Interface': 'axi_stream',
+            }
+            config.config['AcceleratorConfig'] = accel_config
+
+        self.interface = self.config['AcceleratorConfig'].get('Interface', 'axi_stream')  # axi_stream, axi_master, axi_lite
+        self.driver = self.config['AcceleratorConfig'].get('Driver', 'python')  # python or c
+        self.input_type = self.config['AcceleratorConfig']['Precision'].get(
+            'Input', 'float'
+        )  # float, double or ap_fixed<a,b>
+        self.output_type = self.config['AcceleratorConfig']['Precision'].get(
+            'Output', 'float'
+        )  # float, double or ap_fixed<a,b>
+        self.platform = self.config['AcceleratorConfig'].get(
+            'Platform', 'xilinx_u250_xdma_201830_2'
+        )  # Get platform folder name
+
+        assert (
+            len(model_inputs) == 1
+        ), "Only models with one input tensor are currently supported by VitisAcceleratorIPFlowBackend"
+        assert (
+            len(model_outputs) == 1
+        ), "Only models with one output tensor are currently supported by VitisAcceleratorIPFlowBackend"
+        self.inp = model_inputs[0]
+        self.out = model_outputs[0]
+        inp_axi_t = self.input_type
+        out_axi_t = self.output_type
+
+        if inp_axi_t not in ['float', 'double']:
+            self.input_type = self._next_factor8_type(config.backend.convert_precision_string(inp_axi_t))
+        if out_axi_t not in ['float', 'double']:
+            self.output_type = self._next_factor8_type(config.backend.convert_precision_string(out_axi_t))
+
+        if self.input_type == 'float':
+            self.input_bitwidth = 32
+        elif self.input_type == 'double':
+            self.input_bitwidth = 64
+        else:
+            self.input_bitwidth = config.backend.convert_precision_string(inp_axi_t).width
+
+        if out_axi_t == 'float':
+            self.output_bitwidth = 32
+        elif out_axi_t == 'double':
+            self.output_bitwidth = 64
+        else:
+            self.output_bitwidth = config.backend.convert_precision_string(out_axi_t).width
+
+    def _next_factor8_type(self, p):
+        '''Return a new type with the width rounded to the next factor of 8 up to p's width
+        Args:
+            p : IntegerPrecisionType or FixedPrecisionType
+        Returns:
+            An IntegerPrecisionType or FixedPrecisionType with the width rounder up to the next factor of 8
+            of p's width. Other parameters (fractional bits, extra modes) stay the same.
+        '''
+        W = p.width
+        newW = int(np.ceil(W / 8) * 8)
+        if isinstance(p, FixedPrecisionType):
+            return FixedPrecisionType(newW, p.integer, p.signed, p.rounding_mode, p.saturation_mode, p.saturation_bits)
+        elif isinstance(p, IntegerPrecisionType):
+            return IntegerPrecisionType(newW, p.signed)
+
+    def get_io_bitwidth(self):
+        return self.input_bitwidth, self.output_bitwidth
+
+    def get_corrected_types(self):
+        return self.input_type, self.output_type, self.inp, self.out
+
+    def get_interface(self):
+        return self.interface
+
+    def get_board_info(self, board=None):
+        if board is None:
+            board = self.board
+        if board in self.supported_boards.keys():
+            return self.supported_boards[board]
+        else:
+            raise Exception('The board is still not supported')
+
+    def get_part(self):
+        return self.part
+
+    def get_driver(self):
+        return self.driver
+
+    def get_board(self):
+        return self.board
+
+    def get_platform(self):
+        return self.platform
+
+    def get_clock_period(self):
+        return self.clock_period
+
+    def get_driver_path(self):
+        if self.board.startswith('alveo'):
+            return '../templates/vitis_accelerator_ip_flow/' + 'alveo/' + self.driver + '_drivers/' + self.get_driver_file()
+        else:
+            return (
+                '../templates/vitis_accelerator_ip_flow/'
+                + self.board
+                + '/'
+                + self.driver
+                + '_drivers/'
+                + self.get_driver_file()
+            )
+
+    def get_driver_file(self):
+        driver_ext = '.py' if self.driver == 'python' else '.h'
+        return self.interface + '_driver' + driver_ext
+
+    def get_krnl_rtl_src_dir(self):
+        return '../templates/vitis_accelerator_ip_flow/' + 'alveo/' + '/krnl_rtl_src'
+
+    def get_input_type(self):
+        return self.input_type
+
+    def get_output_type(self):
+        return self.output_type
+
+    def get_tcl_file_path(self):
+        board_info = self.get_board_info(self.board)
+        tcl_scripts = board_info.get('tcl_scripts', None)
+        if tcl_scripts is None:
+            raise Exception('No tcl scripts definition available for the board in supported_board.json')
+        tcl_script = tcl_scripts.get(self.interface, None)
+        if tcl_script is None:
+            raise Exception('No tcl script definition available for the desired interface in supported_board.json')
+        if self.board.startswith('alveo'):
+            return '../templates/vitis_accelerator_ip_flow/' + 'alveo/' + '/tcl_scripts/' + tcl_script
+        else:
+            return '../templates/vitis_accelerator_ip_flow/' + self.board + '/tcl_scripts/' + tcl_script

hls4ml/templates/vitis/nnet_utils/nnet_sepconv1d_stream.h

@@ -86,7 +86,7 @@ void separable_conv_1d_cl(hls::stream<data_T> &data, hls::stream<res_T> &res,
     #pragma HLS DATAFLOW
 
     hls::stream<dw_res_T> depthwise_res;
-    unsigned res_depth = CONFIG_T::depthwise_config::out_width;
+    const unsigned res_depth = CONFIG_T::depthwise_config::out_width;
     #pragma HLS STREAM variable=depthwise_res depth=res_depth
 
     depthwise_conv_1d_buffer_cl<data_T, dw_res_T, typename CONFIG_T::depthwise_config>(data, depthwise_res,

hls4ml/templates/vitis/nnet_utils/nnet_sepconv2d_stream.h

@@ -120,7 +120,7 @@ void separable_conv_2d_cl(hls::stream<data_T> &data, hls::stream<res_T> &res,
     #pragma HLS DATAFLOW
 
     hls::stream<dw_res_T> depthwise_res;
-    unsigned res_depth = CONFIG_T::depthwise_config::out_height * CONFIG_T::depthwise_config::out_width;
+    const unsigned res_depth = CONFIG_T::depthwise_config::out_height * CONFIG_T::depthwise_config::out_width;
     #pragma HLS STREAM variable=depthwise_res depth=res_depth
 
     depthwise_conv_2d_buffer_cl<data_T, dw_res_T, typename CONFIG_T::depthwise_config>(data, depthwise_res,