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Run format on generated json_events #293

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Run format on generated json_events #293

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211 changes: 139 additions & 72 deletions hbt/src/perf_event/json_events/generated/CpuArch.h
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Original file line number Diff line number Diff line change
Expand Up @@ -42,39 +42,67 @@ enum class CpuArch {
UNKNOWN
};

inline std::ostream & operator<<(std::ostream & os, CpuArch ev) {
inline std::ostream& operator<<(std::ostream& os, CpuArch ev) {
switch (ev) {
case CpuArch::NEOVERSE_N1: return os << "NEOVERSE_N1";
case CpuArch::NEOVERSE_N2: return os << "NEOVERSE_N2";
case CpuArch::NEOVERSE_V2: return os << "NEOVERSE_V2";
case CpuArch::AMPERE_ONE: return os << "AMPERE_ONE";
case CpuArch::MILAN: return os << "MILAN";
case CpuArch::GENOA: return os << "GENOA";
case CpuArch::BERGAMO: return os << "BERGAMO";
case CpuArch::BDW: return os << "BDW";
case CpuArch::BDW_DE: return os << "BDW-DE";
case CpuArch::BDX: return os << "BDX";
case CpuArch::CLX: return os << "CLX";
case CpuArch::GLM: return os << "GLM";
case CpuArch::HSX: return os << "HSX";
case CpuArch::ICL: return os << "ICL";
case CpuArch::ICX: return os << "ICX";
case CpuArch::IVB: return os << "IVB";
case CpuArch::KNL: return os << "KNL";
case CpuArch::NHM_EX: return os << "NHM-EX";
case CpuArch::SKL: return os << "SKL";
case CpuArch::SKX: return os << "SKX";
case CpuArch::SNB: return os << "SNB";
case CpuArch::SNR: return os << "SNR";
case CpuArch::SPR: return os << "SPR";
case CpuArch::SRF: return os << "SRF";
default: return os << "<UnknownCPU>";
case CpuArch::NEOVERSE_N1:
return os << "NEOVERSE_N1";
case CpuArch::NEOVERSE_N2:
return os << "NEOVERSE_N2";
case CpuArch::NEOVERSE_V2:
return os << "NEOVERSE_V2";
case CpuArch::AMPERE_ONE:
return os << "AMPERE_ONE";
case CpuArch::MILAN:
return os << "MILAN";
case CpuArch::GENOA:
return os << "GENOA";
case CpuArch::BERGAMO:
return os << "BERGAMO";
case CpuArch::BDW:
return os << "BDW";
case CpuArch::BDW_DE:
return os << "BDW-DE";
case CpuArch::BDX:
return os << "BDX";
case CpuArch::CLX:
return os << "CLX";
case CpuArch::GLM:
return os << "GLM";
case CpuArch::HSX:
return os << "HSX";
case CpuArch::ICL:
return os << "ICL";
case CpuArch::ICX:
return os << "ICX";
case CpuArch::IVB:
return os << "IVB";
case CpuArch::KNL:
return os << "KNL";
case CpuArch::NHM_EX:
return os << "NHM-EX";
case CpuArch::SKL:
return os << "SKL";
case CpuArch::SKX:
return os << "SKX";
case CpuArch::SNB:
return os << "SNB";
case CpuArch::SNR:
return os << "SNR";
case CpuArch::SPR:
return os << "SPR";
case CpuArch::SRF:
return os << "SRF";
default:
return os << "<UnknownCPU>";
}
}

// Create CpuArch from CPU information in integers.
inline CpuArch makeCpuArchX86(uint32_t /*vendor_id*/, uint32_t cpu_family_num, uint32_t cpu_model_num, uint32_t cpu_step_num)
{
inline CpuArch makeCpuArchX86(
uint32_t /*vendor_id*/,
uint32_t cpu_family_num,
uint32_t cpu_model_num,
uint32_t cpu_step_num) {
auto cpu_family = makeCpuFamily(cpu_family_num);
if (cpu_family == CpuFamily::AMD) {
switch (cpu_model_num) {
Expand All @@ -85,58 +113,97 @@ inline CpuArch makeCpuArchX86(uint32_t /*vendor_id*/, uint32_t cpu_family_num, u
case 160:
return CpuArch::BERGAMO;
}
}
else if (cpu_family == CpuFamily::INTEL) {
} else if (cpu_family == CpuFamily::INTEL) {
switch (cpu_model_num) {
case 42: return CpuArch::SNB;
case 46: return CpuArch::NHM_EX;
case 58: return CpuArch::IVB;
case 61: return CpuArch::BDW;
case 63: return CpuArch::HSX;
case 71: return CpuArch::BDW;
case 78: return CpuArch::SKL;
case 79: return CpuArch::BDX;
case 42:
return CpuArch::SNB;
case 46:
return CpuArch::NHM_EX;
case 58:
return CpuArch::IVB;
case 61:
return CpuArch::BDW;
case 63:
return CpuArch::HSX;
case 71:
return CpuArch::BDW;
case 78:
return CpuArch::SKL;
case 79:
return CpuArch::BDX;
case 85:
switch (cpu_step_num) {
case 0x0: [[fallthrough]];
case 0x1: [[fallthrough]];
case 0x2: [[fallthrough]];
case 0x3: [[fallthrough]];
case 0x0:
[[fallthrough]];
case 0x1:
[[fallthrough]];
case 0x2:
[[fallthrough]];
case 0x3:
[[fallthrough]];
case 0x4:
return CpuArch::SKX;
case 0x5: [[fallthrough]];
case 0x6: [[fallthrough]];
case 0x7: [[fallthrough]];
case 0x8: [[fallthrough]];
case 0x9: [[fallthrough]];
case 0xA: [[fallthrough]];
case 0xB: [[fallthrough]];
case 0xC: [[fallthrough]];
case 0xD: [[fallthrough]];
case 0xE: [[fallthrough]];
case 0x5:
[[fallthrough]];
case 0x6:
[[fallthrough]];
case 0x7:
[[fallthrough]];
case 0x8:
[[fallthrough]];
case 0x9:
[[fallthrough]];
case 0xA:
[[fallthrough]];
case 0xB:
[[fallthrough]];
case 0xC:
[[fallthrough]];
case 0xD:
[[fallthrough]];
case 0xE:
[[fallthrough]];
case 0xF:
return CpuArch::CLX;
// Step count is extensive. No need for default
} // End of step switch
// Step count is extensive. No need for default
} // End of step switch

case 86: return CpuArch::BDW_DE;
case 87: return CpuArch::KNL;
case 92: return CpuArch::GLM;
case 94: return CpuArch::SKL;
case 95: return CpuArch::GLM;
case 106: return CpuArch::ICX;
case 108: return CpuArch::ICX;
case 125: return CpuArch::ICL;
case 126: return CpuArch::ICL;
case 133: return CpuArch::KNL;
case 134: return CpuArch::SNR;
case 142: return CpuArch::SKL;
case 143: return CpuArch::SPR;
case 158: return CpuArch::SKL;
case 165: return CpuArch::SKL;
case 166: return CpuArch::SKL;
case 175: return CpuArch::SRF;
default: return CpuArch::UNKNOWN;
case 86:
return CpuArch::BDW_DE;
case 87:
return CpuArch::KNL;
case 92:
return CpuArch::GLM;
case 94:
return CpuArch::SKL;
case 95:
return CpuArch::GLM;
case 106:
return CpuArch::ICX;
case 108:
return CpuArch::ICX;
case 125:
return CpuArch::ICL;
case 126:
return CpuArch::ICL;
case 133:
return CpuArch::KNL;
case 134:
return CpuArch::SNR;
case 142:
return CpuArch::SKL;
case 143:
return CpuArch::SPR;
case 158:
return CpuArch::SKL;
case 165:
return CpuArch::SKL;
case 166:
return CpuArch::SKL;
case 175:
return CpuArch::SRF;
default:
return CpuArch::UNKNOWN;
} // End of model switch case
} // End of Intel Family if case

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