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Add string literals and evaluate constant operations #161

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fabianschuiki opened this issue May 11, 2020 · 0 comments
Closed

Add string literals and evaluate constant operations #161

fabianschuiki opened this issue May 11, 2020 · 0 comments
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A-consts Area: Constant evaluation. C-enhancement Category: Adding or improving on features. E-easy Call for Participation: Easy issue, good first issue. L-vlog Language: Verilog and SystemVerilog.
Milestone
v0.11

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@fabianschuiki
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Add strings to src/svlog/value.rs and implement constant evaluation for the basic equality checks on strings.
@fabianschuiki fabianschuiki added E-easy Call for Participation: Easy issue, good first issue. L-vlog Language: Verilog and SystemVerilog. C-enhancement Category: Adding or improving on features. A-consts Area: Constant evaluation. labels May 11, 2020
@fabianschuiki fabianschuiki mentioned this issue May 11, 2020
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@fabianschuiki fabianschuiki changed the title Add string literals and evaluate constants operations Add string literals and evaluate constant operations May 21, 2020
@fabianschuiki fabianschuiki mentioned this issue Jun 15, 2020
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@fabianschuiki fabianschuiki added this to the v0.11 milestone Jun 16, 2020
fabianschuiki added a commit that referenced this issue Sep 4, 2020
@fabianschuiki
svlog: Impl string literals
90dad49 
According to the SV manual, string literals are not of `string` type,
but rather behave like a packed array of bits that is `8*length` wide.
The array holds the ASCII characters of the string, with the first
character in the string appearing at the MSB end (such that assigning to
a variable that is too narrow would truncate the beginning of the
string).

Contributes towards #161.
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A-consts Area: Constant evaluation. C-enhancement Category: Adding or improving on features. E-easy Call for Participation: Easy issue, good first issue. L-vlog Language: Verilog and SystemVerilog.
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