Merge pull request #1705 from antmicro/fix-iob-ppips

071-ppips: add LIOB33 and RIOB33 ppips
f4pga · Jul 8, 2021 · f7f0689 · f7f0689
2 parents 6e6bff0 + ceb0ead
commit f7f0689
Showing 1 changed file with 10 additions and 2 deletions.
diff --git a/fuzzers/071-ppips/generate.tcl b/fuzzers/071-ppips/generate.tcl
@@ -27,7 +27,7 @@ route_design
 write_checkpoint -force design.dcp
 # write_bitstream -force design.bit
 
-proc write_clb_ppips_db {filename tile} {
+proc write_common_ppips_db {filename tile} {
     set fp [open $filename "w"]
     set tile [get_tiles $tile]
     set tile_type [get_property TILE_TYPE $tile]
@@ -292,7 +292,7 @@ foreach tile_type {CLBLM_L CLBLM_R CLBLL_L CLBLL_R} {
     set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
     if {[llength $tiles] != 0} {
         set tile [lindex $tiles 0]
-        write_clb_ppips_db "ppips_[string tolower $tile_type].db" $tile
+        write_common_ppips_db "ppips_[string tolower $tile_type].db" $tile
     }
 }
 
@@ -391,3 +391,11 @@ foreach tile_type {PCIE_INT_INTERFACE_L PCIE_INT_INTERFACE_R} {
         write_pcie_int_interface_ppips_db "ppips_[string tolower $tile_type].db" $tile $allow_wires $forbid_wires
     }
 }
+
+foreach tile_type {RIOB33 LIOB33 RIOB33_SING LIOB33_SING} {
+    set tiles [get_tiles -filter "TILE_TYPE == $tile_type"]
+    if {[llength $tiles] != 0} {
+        set tile [lindex $tiles 0]
+        write_common_ppips_db "ppips_[string tolower $tile_type].db" $tile
+    }
+}