simplify determining idle qubits

ewinston · Oct 5, 2022 · 02e704f · 02e704f
1 parent 753a637
commit 02e704f
Showing 1 changed file with 8 additions and 7 deletions.
diff --git a/qiskit/transpiler/passes/routing/utils.py b/qiskit/transpiler/passes/routing/utils.py
@@ -48,7 +48,8 @@ def route_cf_multiblock(tpass, cf_opnode, current_layout, qregs, root_dag, seed=
     block_layouts = []  # control flow layouts
     # expand to full width for routing
     cf_op = cf_opnode.op
-    order = [root_dag.qubits.index(bit) for bit in cf_opnode.qargs]
+    indices = {bit: i for i, bit in enumerate(root_dag.qubits)}
+    order = [indices[bit] for bit in cf_opnode.qargs]
     for block in cf_op.blocks:
         full_dag_block = root_dag.copy_empty_like()
         dag_block = circuit_to_dag(block)
@@ -61,7 +62,7 @@ def route_cf_multiblock(tpass, cf_opnode, current_layout, qregs, root_dag, seed=
     maxind = np.argmax(depth_cnt)
     block_circuits = [None] * len(block_layouts)
     p2v = current_layout.get_physical_bits()
-    idle_qubits = [None] * len(block_dags)
+    idle_qubits = set(root_dag.qubits)
     for i, updated_dag_block in enumerate(block_dags):
         if i == maxind:
             block_circuits[i] = dag_to_circuit(updated_dag_block)
@@ -79,11 +80,10 @@ def route_cf_multiblock(tpass, cf_opnode, current_layout, qregs, root_dag, seed=
                 ]
                 virtual_swap_dag.compose(physical_swap_dag, qubits=order)
                 updated_dag_block.compose(virtual_swap_dag)
-        idle_qubits[i] = set(root_dag.qubits) & set(updated_dag_block.idle_wires())
-    cfop_idle_qubits = set.intersection(*map(set, idle_qubits))
+        idle_qubits &= set(updated_dag_block.idle_wires())
     # contract idle bits from full width post routing
     for i, updated_dag_block in enumerate(block_dags):
-        updated_dag_block.remove_qubits(*cfop_idle_qubits)
+        updated_dag_block.remove_qubits(*idle_qubits)
         new_dag_block = DAGCircuit()
         new_num_qubits = updated_dag_block.num_qubits()
         qreg = QuantumRegister(new_num_qubits, "q")
@@ -96,7 +96,7 @@ def route_cf_multiblock(tpass, cf_opnode, current_layout, qregs, root_dag, seed=
         block_circuits[i] = dag_to_circuit(new_dag_block)
 
     final_layout = block_layouts[maxind]
-    return cf_op.replace_blocks(block_circuits), final_layout, cfop_idle_qubits
+    return cf_op.replace_blocks(block_circuits), final_layout, idle_qubits
 
 
 def route_cf_looping(tpass, cf_opnode, current_layout, root_dag, seed=None):
@@ -128,7 +128,8 @@ def route_cf_looping(tpass, cf_opnode, current_layout, root_dag, seed=None):
     # expand to full width for routing
     full_dag_block = root_dag.copy_empty_like()
     start_layout = current_layout
-    order = [root_dag.qubits.index(bit) for bit in cf_opnode.qargs]
+    indices = {bit: i for i, bit in enumerate(root_dag.qubits)}
+    order = [indices[bit] for bit in cf_opnode.qargs]
     full_dag_block.compose(dag_block, qubits=order)
     updated_dag_block = tpass.run(full_dag_block)
     updated_layout = tpass.property_set["final_layout"].copy()