ci: add esp32c5 tests to the pipeline

espressif · Aug 8, 2024 · 847aee5 · 847aee5
1 parent 31c4e8b
commit 847aee5
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Showing 6 changed files with 42 additions and 1 deletion.
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
@@ -306,6 +306,7 @@ create_coverage_reports:
     - job: tests_armhf_esp32c2
     - job: tests_armhf_esp32c3
     - job: tests_armhf_esp32c3_flash_encrypted
+    - job: tests_armhf_esp32c5
     - job: tests_armhf_esp32c6
     - job: tests_armhf_esp32h2
     - job: test_nuttx_esp32

diff --git a/.gitlab/ci/build-test-app.yml b/.gitlab/ci/build-test-app.yml
@@ -227,6 +227,14 @@ build_test_app_esp32c3:
     TEST_APP_CONFIGS: "single_core single_core_encrypted svtrace_single apptrace_gcov_single single_core_amazon_freertos"
   extends: .build_idf_master_test_app_template
 
+build_test_app_esp32c5:
+  variables:
+    CHIP_NAME: "esp32c5"
+    TOOLCHAIN_PREFIX: "riscv32-esp"
+    BUILD_TEST_APP_DIR: "build_test_app_esp32c5"
+    TEST_APP_CONFIGS: "single_core svtrace_single apptrace_gcov_single single_core_amazon_freertos"
+  extends: .build_idf_master_test_app_template
+
 build_test_app_esp32c6:
   variables:
     CHIP_NAME: "esp32c6"

diff --git a/.gitlab/ci/test.yml b/.gitlab/ci/test.yml
@@ -227,6 +227,18 @@ tests_armhf_esp32c3_flash_encrypted:
     CHIP_NAME: "esp32c3"
     TEST_RUN_EXTRA_OPTS: "-i latest -b esp32c3-ftdi -p test_*.*SingleEncrypted"
 
+tests_armhf_esp32c5:
+  extends: .tests_armhf_master_riscv_template
+  tags:
+    - esp32c5
+    - usb_serial_jtag
+  needs:
+    - job: build_test_app_esp32c5
+    - job: build_linux_armhf_test
+  variables:
+    CHIP_NAME: "esp32c5"
+    TEST_RUN_EXTRA_OPTS: "-i latest -b esp32c5-builtin -p test_*.*Single -e test_special*.*Single"
+
 tests_armhf_esp32c6:
   extends: .tests_armhf_master_riscv_template
   tags:

diff --git a/tcl/target/esp32c5.cfg b/tcl/target/esp32c5.cfg
@@ -13,7 +13,7 @@ set _ESP_ARCH                   "riscv"
 set _ONLYCPU                    0x01
 set _LP_TAPNUM                  1
 set _HP_TAPNUM                  1
-set _ESP_EFUSE_MAC_ADDR_REG     0x600B0844
+set _ESP_EFUSE_MAC_ADDR_REG     0x600B4844
 
 # Set workarea address and size
 # stub flasher may need a lot of memory in case of compressed writes to flash (~107KB):

diff --git a/testing/esp/run_tests.py b/testing/esp/run_tests.py
@@ -82,6 +82,22 @@
         'chip_name' : 'esp32c3',
         'target_triple' : 'riscv32-esp-elf'
     },
+    'esp32c5-ftdi' :  {
+        'files' : [
+            os.path.join('board', 'esp32c5-ftdi.cfg')
+        ],
+        'commands' : [],
+        'chip_name' : 'esp32c5',
+        'target_triple' : 'riscv32-esp-elf'
+    },
+    'esp32c5-builtin' :  {
+        'files' : [
+            os.path.join('board', 'esp32c5-builtin.cfg')
+        ],
+        'commands' : [],
+        'chip_name' : 'esp32c5',
+        'target_triple' : 'riscv32-esp-elf'
+    },
     'esp32c6-ftdi' :  {
         'files' : [
             os.path.join('board', 'esp32c6-ftdi.cfg')

diff --git a/testing/esp/test_bp.py b/testing/esp/test_bp.py
@@ -29,6 +29,10 @@ def setUp(self):
             # esp32c6 has 4 HW breakpoint slots
             # 2 dummy HW breaks to fill in HW breaks slots and make OpenOCD using SW breakpoints in flash (seen as HW ones by GDB)
             self.bps = ['unused_func0', 'unused_func1']
+        elif testee_info.chip == "esp32c5":
+            # esp32c5 has 3 HW breakpoint slots
+            # 1 dummy HW break to fill in HW breaks slots and make OpenOCD using SW breakpoints in flash (seen as HW ones by GDB)
+            self.bps = ['unused_func0']
         # + 2 HW breaks + 1 flash SW break + RAM SW break
         self.bps += ['app_main', 'gpio_set_direction', 'gpio_set_level', 'vTaskDelay']