tcl/target: add ESP_ONLYCPU command

.gitlab/ci/test-sanitizers.yml

@@ -401,7 +401,7 @@ test_sanitizers_nuttx_esp32:
     ESP_GDB_TOOLCHAIN: "${ESP_XTENSA_GDB_TOOLCHAIN}"
     TEST_RUN_DIR: "nuttx_test"
     NUTTX_APP_NAME: "nuttx_openocd"
-    OOCD_CMDS: "set ESP_RTOS nuttx,set ESP32_ONLYCPU 1"
+    OOCD_CMDS: "set ESP_RTOS nuttx,set ESP_ONLYCPU 1"
     TEST_RUN_EXTRA_OPTS: "-i other -b esp32-wrover-kit-3.3v -p test_nuttx -e *.*Encrypted"
   needs:
     - job: build_linux_armhf_sanitizer_test

.gitlab/ci/test.yml

@@ -668,7 +668,7 @@ tests_linux_simple_esp32:
     ESP_GDB_TOOLCHAIN: "${ESP_XTENSA_GDB_TOOLCHAIN}"
     TEST_RUN_DIR: "nuttx_test"
     NUTTX_APP_NAME: "nuttx_openocd"
-    OOCD_CMDS: "set ESP_RTOS nuttx,set ESP32_ONLYCPU 1"
+    OOCD_CMDS: "set ESP_RTOS nuttx,set ESP_ONLYCPU 1"
     TEST_RUN_EXTRA_OPTS: "-i other -b ${TEST_BOARD} -p test_nuttx -e *.*Encrypted"
   needs:
     - job: build_linux_armhf_test

espressif.md

@@ -12,12 +12,12 @@ The folowing configuration variables are common for all Espressif chips:
 * `ESP_RTOS` - the name of RTOS running on the target. Default is 'FreeRTOS'. To disable OS support (for bare metal system) use 'none'.
 * `ESP_FLASH_SIZE` - size of the chip's flash. Default is 'auto'. To disable flash functionality set to '0'.
 * `ESP_SEMIHOST_BASEDIR` - base dir for semihosting I/O. Default is OpenOCD's current working directory.
+* `ESP_ONLYCPU` - the mask indicating which cores are enabled for debugging. Default is '3' for ESP32 and ESP32-S3.
+  Set to '1' for single core debugging.
 
 ### ESP32 Options
 
 The folowing configuration variables are common for ESP32 family chips:
-* `ESP32_ONLYCPU` - the mask indicating which cores are enabled for debugging. Default is '3'. 
-  Set to '1' for single core debugging.
 * `ESP32_FLASH_VOLTAGE` - tell OpenOCD which SPI flash voltage is used by the board (3.3 or 1.8)
   The TDI pin of ESP32 is also a bootstrap pin that selects the voltage the SPI flash
   chip runs at. When a hard reset happens (e.g. because someone switches the board off

tcl/target/esp32-solo-1.cfg

@@ -3,7 +3,7 @@
 # Example OpenOCD configuration file for ESP32-SOLO-1 module.
 
 # Single core version of ESP32
-set ESP32_ONLYCPU 1
+set ESP_ONLYCPU 1
 
 # Source the ESP32 configuration file
 source [find target/esp32.cfg]

tcl/target/esp32.cfg

@@ -8,15 +8,20 @@ source [find target/esp_common.cfg]
 set _CHIPNAME 					"esp32"
 set _CPUTAPID 					0x120034e5
 set _ESP_ARCH 					"xtensa"
-set _ONLYCPU					3
 set _ESP_SMP_TARGET				1
 set _ESP_SMP_BREAK 				1
 set _ESP_EFUSE_MAC_ADDR_REG 	0x3ff5A004
 
 if { [info exists ESP32_ONLYCPU] } {
+	echo "ESP32_ONLYCPU command will be deprecated! Use ESP_ONLYCPU instead."
 	set _ONLYCPU $ESP32_ONLYCPU
 }
 
+# if not set until now, set as default dual core
+if { ![info exists _ONLYCPU] } {
+	set _ONLYCPU 3
+}
+
 set _FLASH_VOLTAGE 3.3
 if { [info exists ESP32_FLASH_VOLTAGE] } {
 	set _FLASH_VOLTAGE $ESP32_FLASH_VOLTAGE

tcl/target/esp32s3.cfg

@@ -8,15 +8,20 @@ source [find target/esp_common.cfg]
 set _CHIPNAME 					"esp32s3"
 set _CPUTAPID 					0x120034e5
 set _ESP_ARCH 					"xtensa"
-set _ONLYCPU					3
 set _ESP_SMP_TARGET				1
 set _ESP_SMP_BREAK 				1
 set _ESP_EFUSE_MAC_ADDR_REG  	0x60007044
 
 if { [info exists ESP32_S3_ONLYCPU] } {
+	echo "ESP32_S3_ONLYCPU command will be deprecated! Use ESP_ONLYCPU instead."
 	set _ONLYCPU $ESP32_S3_ONLYCPU
 }
 
+# if not set until now, set as default dual core
+if { ![info exists _ONLYCPU] } {
+	set _ONLYCPU 3
+}
+
 # Set workarea address and size
 # Keep in mind 2x16KB area (0x3FCD0000..0x3FCD3FFF and 0x3FCE0000..0x3FCE3FFF) is reserved for the apptrace blocks
 set _WA_ADDR				0x3FC9C000

tcl/target/esp_common.cfg

@@ -42,6 +42,10 @@ if { [info exists ESP_IDF_HOST] } {
 	set _ESP_IDF_HOST $ESP_IDF_HOST
 }
 
+if { [info exists ESP_ONLYCPU] } {
+	set _ONLYCPU $ESP_ONLYCPU
+}
+
 proc set_esp_common_variables { } {
 	global _CHIPNAME _ONLYCPU _ESP_SMP_TARGET
 	global _CPUNAME_0 _CPUNAME_1 _TARGETNAME_0 _TARGETNAME_1 _TAPNAME_0 _TAPNAME_1