esp32c3: Reset target upon GDB connection if memory protection is ena…

…bled Closes #176 Closes #183
espressif · Nov 3, 2021 · 1e8fb85 · 1e8fb85
1 parent 433ad9a
commit 1e8fb85
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Showing 3 changed files with 51 additions and 4 deletions.
diff --git a/tcl/mmr_helpers.tcl b/tcl/mmr_helpers.tcl
@@ -70,3 +70,22 @@ proc show_mmr_bitfield { MSB LSB VAL FIELDNAME FIELDVALUES } {
     }
     echo [format "%-15s: %d (0x%0*x) %s" $FIELDNAME $nval $width $nval $sval ]
 }
+
+# Give: ADDR - address of the register.
+#       BIT - bit's number.
+
+proc mmr_get_bit { ADDR BIT } {
+	set val [memread32 $ADDR]
+    set bit_val [expr $val & [expr 1 << $BIT]]
+    return $bit_val
+}
+
+
+# Give: ADDR - address of the register.
+#       MSB - MSB bit's number.
+#       LSB - LSB bit's number.
+
+proc mmr_get_bitfield { ADDR MSB LSB } {
+	set rval [memread32 $ADDR]
+    return normalize_bitfield $rval $MSB $LSB
+}
diff --git a/tcl/target/esp32c3.cfg b/tcl/target/esp32c3.cfg
@@ -1,6 +1,10 @@
 # The ESP32-C3 only supports JTAG.
 transport select jtag
 
+set CPU_MAX_ADDRESS 0xFFFFFFFF
+source [find bitsbytes.tcl]
+source [find memory.tcl]
+source [find mmr_helpers.tcl]
 # Source the ESP common configuration file
 source [find target/esp_common.cfg]
 
@@ -73,6 +77,26 @@ proc esp32c3_soc_reset { } {
     riscv dmi_write 0x10 0x80000003
 }
 
+proc esp32c3_memprot_is_enabled { } {
+    # IRAM0 mon, SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG
+    if { [mmr_get_bit 0x600C10E8 1] != 0 } {
+        return 1
+    }
+    # DRAM0 mon, SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG
+    if { [mmr_get_bit 0x600C1108 1] != 0 } {
+        return 1
+    }
+    # IRAM0 permissions, SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG
+    if { [mmr_get_bitfield 0x600C10E0 11 0] != 0 } {
+        return 1
+    }
+    # DRAM0 permissions, SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG
+    if { [mmr_get_bitfield 0x600C1100 7 0] != 0 } {
+        return 1
+    }
+    return 0
+}
+
 
 if { $_RTOS == "none" } {
     target create $_TARGETNAME esp32c3 -chain-position $_TAPNAME
@@ -81,7 +105,9 @@ if { $_RTOS == "none" } {
 }
 
 $_TARGETNAME configure -event reset-assert-post { esp32c3_soc_reset }
-$_TARGETNAME configure -event halted { esp32c3_wdt_disable }
+$_TARGETNAME configure -event halted {
+    esp32c3_wdt_disable
+}
 $_TARGETNAME configure -event examine-end {
     # Need this to handle 'apptrace init' syscall correctly because semihosting is not enabled by default
     arm semihosting enable
@@ -90,6 +116,11 @@ $_TARGETNAME configure -event examine-end {
 $_TARGETNAME configure -event gdb-attach {
     # 'halt' is necessary to auto-probe flash bank when GDB is connected and generate proper memory map
     halt
+    if { [esp32c3_memprot_is_enabled] } {
+        # 'reset halt' to disable memory protection and allow flasher to work correctly
+        echo "Memory protection is enabled. Reset target to disable it..."
+        reset halt
+    }
     # by default mask interrupts while stepping
     riscv maskisr steponly
 }

diff --git a/testing/esp/test_apps/gen_ut_app/configs/apptrace_gcov_single b/testing/esp/test_apps/gen_ut_app/configs/apptrace_gcov_single
@@ -8,6 +8,3 @@ CONFIG_ESP32_APPTRACE_POSTMORTEM_FLUSH_TRAX_THRESH=0
 CONFIG_ESP32_APPTRACE_PENDING_DATA_SIZE_MAX=0
 CONFIG_ESP32_GCOV_ENABLE=y
 CONFIG_ESP32_DEBUG_STUBS_ENABLE=y
-
-CONFIG_ESP32S2_MEMPROT_FEATURE=n
-CONFIG_ESP32S2_MEMPROT_FEATURE_LOCK=n