esp/semihost: Adds generic semihost ops interface for all ESP chips

src/target/esp.h

@@ -81,4 +81,12 @@ struct esp_dbg_stubs {
 	struct esp_dbg_stubs_desc desc;
 };
 
+/**
+ * Semihost calls handling operations.
+ */
+struct esp_semihost_ops {
+	/** Callback called before handling semihost call */
+	int (*prepare)(struct target *target);
+};
+
 #endif	/* _ESP_H */

src/target/esp32.c

@@ -595,7 +595,7 @@ static const struct esp_xtensa_smp_chip_ops esp32_chip_ops = {
 	.reset = esp32_soc_reset
 };
 
-static const struct esp_xtensa_semihost_ops esp32_semihost_ops = {
+static const struct esp_semihost_ops esp32_semihost_ops = {
 	.prepare = esp32_disable_wdts
 };
 

src/target/esp32c3.c

@@ -55,7 +55,7 @@ static int esp_riscv_semihosting_post_result(struct target *target)
 	struct semihosting *semihosting = target->semihosting;
 	if (!semihosting) {
 		/* If not enabled, silently ignored. */
-		return 0;
+		return ERROR_OK;
 	}
 
 	LOG_DEBUG("0x%" PRIx64, semihosting->result);
@@ -66,7 +66,7 @@ static int esp_riscv_semihosting_post_result(struct target *target)
 	riscv_set_register(target, GDB_REGNO_PC, new_pc);
 
 	riscv_set_register(target, GDB_REGNO_A0, semihosting->result);
-	return 0;
+	return ERROR_OK;
 }
 
 static int esp32c3_wdt_disable(struct target *target)
@@ -110,10 +110,13 @@ static int esp32c3_wdt_disable(struct target *target)
 int esp_riscv_semihosting(struct target *target)
 {
 	int res = ERROR_OK;
+	struct esp_riscv_common *esp_riscv = target_to_esp_riscv(target);
 	struct semihosting *semihosting = target->semihosting;
 
 	LOG_DEBUG("enter");
-	esp32c3_wdt_disable(target);
+	if (esp_riscv->semi_ops && esp_riscv->semi_ops->prepare)
+		esp_riscv->semi_ops->prepare(target);
+
 	if (semihosting->op == ESP_RISCV_APPTRACE_SYSNR) {
 		res = esp_riscv_apptrace_info_init(target, semihosting->param);
 		if (res != ERROR_OK)
@@ -131,6 +134,10 @@ int esp_riscv_semihosting(struct target *target)
 	return res;
 }
 
+static const struct esp_semihost_ops esp32c3_semihost_ops = {
+	.prepare = esp32c3_wdt_disable
+};
+
 static int esp32c3_init_target(struct command_context *cmd_ctx,
 	struct target *target)
 {
@@ -139,7 +146,10 @@ static int esp32c3_init_target(struct command_context *cmd_ctx,
 	if (!esp32c3)
 		return ERROR_FAIL;
 	target->arch_info = esp32c3;
-	return esp_riscv_init_target_info(cmd_ctx, target, &esp32c3->esp_riscv);
+	return esp_riscv_init_target_info(cmd_ctx,
+		target,
+		&esp32c3->esp_riscv,
+		&esp32c3_semihost_ops);
 }
 
 static void esp32c3_deinit_target(struct target *target)
@@ -320,29 +330,6 @@ static int esp32c3_deassert_reset(struct target *target)
 	return riscv_target.deassert_reset(target);
 }
 
-static int esp32c3_check_reset(struct target *target)
-{
-	/* if (target->state != TARGET_HALTED) { */
-	/*      / * Need this to configure core to handle ebreak via debugger and handle 'apptrace */
-	/*       * init' syscall correctly. * / */
-	/*      / * We can write core debug register DCSR in HALTED state only, fortunately RISCV */
-	/*       * generic code enables ebreaks on every resume/step, * / */
-	/*      / * so we just halt and resume target * / */
-	/*      LOG_DEBUG("Halt target to enable ebreaks."); */
-	/*      int ret = target_halt(target); */
-	/*      if (ret != ERROR_OK) */
-	/*              return ret; */
-	/*      ret = target_wait_state(target, TARGET_HALTED, 500); */
-	/*      if (ret != ERROR_OK) */
-	/*              return ret; */
-	/*      ret = target_resume(target, 1, 0, 0, 0); */
-	/*      if (ret != ERROR_OK) */
-	/*              return ret; */
-	/* } */
-
-	return ERROR_OK;
-}
-
 static int esp32c3_read_memory(struct target *target, target_addr_t address,
 	uint32_t size, uint32_t count, uint8_t *buffer)
 {
@@ -457,7 +444,6 @@ struct target_type esp32c3_target = {
 
 	.assert_reset = esp32c3_assert_reset,
 	.deassert_reset = esp32c3_deassert_reset,
-	.check_reset = esp32c3_check_reset,
 
 	.read_memory = esp32c3_read_memory,
 	.write_memory = esp32c3_write_memory,

src/target/esp32s2.c

@@ -691,7 +691,7 @@ static const struct esp_xtensa_flash_breakpoint_ops esp32s2_spec_brp_ops = {
 	.breakpoint_remove = esp_xtensa_flash_breakpoint_remove
 };
 
-static const struct esp_xtensa_semihost_ops esp32s2_semihost_ops = {
+static const struct esp_semihost_ops esp32s2_semihost_ops = {
 	.prepare = esp32s2_disable_wdts
 };
 

src/target/esp32s3.c

@@ -601,7 +601,7 @@ static const struct esp_xtensa_smp_chip_ops esp32s3_chip_ops = {
 	.reset = esp32s3_soc_reset
 };
 
-static const struct esp_xtensa_semihost_ops esp32s3_semihost_ops = {
+static const struct esp_semihost_ops esp32s3_semihost_ops = {
 	.prepare = esp32s3_disable_wdts
 };
 

src/target/esp_riscv.h

@@ -31,18 +31,19 @@ struct esp_riscv_common {
 	riscv_info_t riscv;
 	struct esp_riscv_apptrace_info apptrace;
 	struct esp_dbg_stubs dbg_stubs;
+	struct esp_semihost_ops *semi_ops;
 };
 
 static inline struct esp_riscv_common *target_to_esp_riscv(const struct target *target)
 {
 	return target->arch_info;
 }
 
-static inline int esp_riscv_init_target_info(struct command_context *cmd_ctx,
-	struct target *target,
-	struct esp_riscv_common *esp_riscv)
+static inline int esp_riscv_init_target_info(struct command_context *cmd_ctx, struct target *target,
+	struct esp_riscv_common *esp_riscv, const struct esp_semihost_ops *semi_ops)
 {
 	esp_riscv->apptrace.hw = &esp_riscv_apptrace_hw;
+	esp_riscv->semi_ops = (struct esp_semihost_ops *)semi_ops;
 	return riscv_init_target_info(cmd_ctx, target, &esp_riscv->riscv);
 }
 

src/target/esp_xtensa.c

@@ -165,12 +165,12 @@ int esp_xtensa_init_arch_info(struct target *target,
 	const struct xtensa_config *xtensa_cfg,
 	struct xtensa_debug_module_config *dm_cfg,
 	const struct esp_xtensa_flash_breakpoint_ops *flash_brps_ops,
-	const struct esp_xtensa_semihost_ops *semihost_ops)
+	const struct esp_semihost_ops *semihost_ops)
 {
 	int ret = xtensa_init_arch_info(target, &esp_xtensa->xtensa, xtensa_cfg, dm_cfg);
 	if (ret != ERROR_OK)
 		return ret;
-	esp_xtensa->semihost.ops = (struct esp_xtensa_semihost_ops *)semihost_ops;
+	esp_xtensa->semihost.ops = (struct esp_semihost_ops *)semihost_ops;
 	esp_xtensa->flash_brps_ops = flash_brps_ops;
 	esp_xtensa->flash_brps =
 		calloc(ESP_XTENSA_FLASH_BREAKPOINTS_MAX_NUM,

src/target/esp_xtensa.h

@@ -44,15 +44,11 @@ struct esp_xtensa_flash_breakpoint_ops {
 		struct esp_xtensa_flash_breakpoint *spec_bp);
 };
 
-struct esp_xtensa_semihost_ops {
-	int (*prepare)(struct target *target);
-};
-
 struct esp_xtensa_semihost_data {
 	char *basedir;
 	uint32_t version;		/* sending with drvinfo syscall */
 	bool need_resume;
-	struct esp_xtensa_semihost_ops *ops;
+	struct esp_semihost_ops *ops;
 };
 
 struct esp_xtensa_common {
@@ -74,7 +70,7 @@ int esp_xtensa_init_arch_info(struct target *target,
 	const struct xtensa_config *xtensa_cfg,
 	struct xtensa_debug_module_config *dm_cfg,
 	const struct esp_xtensa_flash_breakpoint_ops *spec_brps_ops,
-	const struct esp_xtensa_semihost_ops *semihost_ops);
+	const struct esp_semihost_ops *semihost_ops);
 int esp_xtensa_target_init(struct command_context *cmd_ctx, struct target *target);
 void esp_xtensa_target_deinit(struct target *target);
 int esp_xtensa_arch_state(struct target *target);

src/target/esp_xtensa_smp.c

@@ -555,7 +555,7 @@ int esp_xtensa_smp_init_arch_info(struct target *target,
 	struct xtensa_debug_module_config *dm_cfg,
 	const struct esp_xtensa_flash_breakpoint_ops *flash_brps_ops,
     const struct esp_xtensa_smp_chip_ops *chip_ops,
-	const struct esp_xtensa_semihost_ops *semihost_ops)
+	const struct esp_semihost_ops *semihost_ops)
 {
 	int ret = esp_xtensa_init_arch_info(target, &esp_xtensa_smp->esp_xtensa, xtensa_cfg, dm_cfg, flash_brps_ops, semihost_ops);
 	if (ret != ERROR_OK)

src/target/esp_xtensa_smp.h

@@ -62,7 +62,7 @@ int esp_xtensa_smp_init_arch_info(struct target *target,
 	struct xtensa_debug_module_config *dm_cfg,
 	const struct esp_xtensa_flash_breakpoint_ops *flash_brps_ops,
     const struct esp_xtensa_smp_chip_ops *chip_ops,
-	const struct esp_xtensa_semihost_ops *semihost_ops);
+	const struct esp_semihost_ops *semihost_ops);
 int esp_xtensa_smp_run_func_image(struct target *target,
 	struct xtensa_algo_run_data *run,
 	struct xtensa_algo_image *image,