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target/esp_riscv: add medeleg reg to esp32c6 and h2 #8

target/esp_riscv: add medeleg reg to esp32c6 and h2

target/esp_riscv: add medeleg reg to esp32c6 and h2 #8

Test OpenOCD  /  Test OpenOCD on Linux

succeeded Apr 12, 2024 in 5s