Xtensa patches (11.x) (Do not merge, PR created for easier review only) (LLVM-89) #42
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Add Xtensa.td, XtensaInstrInfo.td etc. Currently add just part of Core Instructions like ALU, processor control, memory barrier and some move instructions. Add instructions formats and basic registers.
Add FDE CFI encoding for Xtensa.
Add instruction printer and basic tests of the Xtensa instructions.
Add relocations and fixups support in object files generation. Modify tests to support new instructions. Add tests for relocations and fixups.
Lower ConstantPool, GlobalAddress, BlockAddress and JumpTable. Implement lowering of External and JumpTable symbols to MCInst representation.
Also lower SHL, SRA, SRL with register operands.
Implement load unsigned 8-bit pseudo operation. Implement extending loads patterns extloadi1/i8/i16.
Make backend initialize functions public and visible outside library.
Add FP instructions test, format FP instruction descriptions.
Remove register class for boolean operands, because it is only suitable for FP compare operations and may lead to problems in other cases. Disable load width reduction, because for IRAM memory it may cause exceptions.
Closed
This was referenced Dec 7, 2020
Do not use Frame Pointer by default. Also improve storing function argument from a7 register to a8 register. Corrected funnel shift test. Closes #19
Remove redundant bits from CALLX/RET descriptions.
Signed-off-by: Andrei Safronov <[email protected]>
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changed the title
Modified linker options. Added "no-rtti" directory to library search path in case of -fno-rtti option is in arguments. Added "-lgcc" option.
Add job which builds toolchain for windows.
Change gcc toolchain release and use new version of the build scripts.
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This PR allows reviewing Xtensa patches on top of release/11.x branch.