feat(esp32h2): Enable USB-JTAG/Serial mode in the stub flasher

espressif · Jan 31, 2023 · 0d2e17f · 0d2e17f
1 parent 4c99854
commit 0d2e17f
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Showing 3 changed files with 40 additions and 10 deletions.
diff --git a/flasher_stub/include/rom_functions.h b/flasher_stub/include/rom_functions.h
@@ -18,11 +18,11 @@ int uart_rx_one_char(uint8_t *ch);
 uint8_t uart_rx_one_char_block();
 int uart_tx_one_char(char ch);
 
-#if ESP32C6
+#if ESP32C6 || ESP32H2
 /* uart_tx_one_char doesn't send data to USB device serial, needs to be replaced */
 int uart_tx_one_char2(char ch);
 #define uart_tx_one_char(ch) uart_tx_one_char2(ch)
-#endif // ESP32C6
+#endif // ESP32C6 || ESP32H2
 
 void uart_div_modify(uint32_t uart_no, uint32_t baud_div);
 

diff --git a/flasher_stub/include/soc_support.h b/flasher_stub/include/soc_support.h
@@ -50,6 +50,11 @@
 #define IS_RISCV 1
 #endif // ESP32C6
 
+#ifdef ESP32H2
+#define WITH_USB_JTAG_SERIAL 1
+#define IS_RISCV 1
+#endif // ESP32H2
+
 // Increase CPU freq to speed up read/write operations over USB
 #define USE_MAX_CPU_FREQ (WITH_USB_JTAG_SERIAL || WITH_USB_OTG)
 
@@ -139,10 +144,13 @@
 #endif
 
 #ifdef ESP32H2
-#define UART_BASE_REG      0x60000000 /* UART0 */
-#define SPI_BASE_REG       0x60003000 /* SPI peripheral 1, used for SPI flash */
-#define SPI0_BASE_REG      0x60002000 /* SPI peripheral 0, inner state machine */
-#define GPIO_BASE_REG      0x60091000
+#define UART_BASE_REG       0x60000000 /* UART0 */
+#define SPI_BASE_REG        0x60003000 /* SPI peripheral 1, used for SPI flash */
+#define SPI0_BASE_REG       0x60002000 /* SPI peripheral 0, inner state machine */
+#define GPIO_BASE_REG       0x60091000
+#define USB_DEVICE_BASE_REG 0x6000F000
+#define DR_REG_PCR_BASE     0x60096000
+#define DR_REG_LP_WDT_BASE  0x600B1C00
 #endif
 
 /**********************************************************
@@ -277,11 +285,20 @@
 #define UART_USB_JTAG_SERIAL  3
 
 #define DR_REG_INTERRUPT_MATRIX_BASE            0x60010000
-#define INTERRUPT_CORE0_USB_INTR_MAP_REG        (DR_REG_INTERRUPT_MATRIX_BASE + 0xC0) /* USB-JTAG-Serial, INTMTX_CORE0_USB_INT_MAP_REG */
+#define INTERRUPT_CORE0_USB_INTR_MAP_REG        (DR_REG_INTERRUPT_MATRIX_BASE + 0xC0) /* USB-JTAG-Serial, INTMTX_CORE0_USB_INTR_MAP_REG */
 
 #define ETS_USB_INUM 17  /* arbitrary level 1 level interrupt */
 #endif // ESP32C6
 
+#ifdef ESP32H2
+#define UART_USB_JTAG_SERIAL  3
+
+#define DR_REG_INTERRUPT_MATRIX_BASE            0x60010000
+#define INTERRUPT_CORE0_USB_INTR_MAP_REG        (DR_REG_INTERRUPT_MATRIX_BASE + 0x94) /* USB-JTAG-Serial, INTMTX_CORE0_USB_INTR_MAP_REG */
+
+#define ETS_USB_INUM 17  /* arbitrary level 1 level interrupt */
+#endif // ESP32H2
+
 #ifdef WITH_USB_JTAG_SERIAL
 #define USB_DEVICE_INT_ENA_REG          (USB_DEVICE_BASE_REG + 0x010)
 #define USB_DEVICE_INT_CLR_REG          (USB_DEVICE_BASE_REG + 0x014)
@@ -320,6 +337,11 @@
 #define RTC_CNTL_WDTWPROTECT_REG      (DR_REG_LP_WDT_BASE + 0x0018)  // LP_WDT_RWDT_WPROTECT_REG
 #endif
 
+#ifdef ESP32H2
+#define RTC_CNTL_WDTCONFIG0_REG       (DR_REG_LP_WDT_BASE + 0x0)   // LP_WDT_RWDT_CONFIG0_REG
+#define RTC_CNTL_WDTWPROTECT_REG      (DR_REG_LP_WDT_BASE + 0x0018)  // LP_WDT_RWDT_WPROTECT_REG
+#endif
+
 #define RTC_CNTL_WDT_WKEY             0x50D83AA1
 #define RTC_CNTL_FORCE_DOWNLOAD_BOOT  (1 << 0)
 
@@ -377,6 +399,14 @@
 #define PCR_SOC_CLK_MAX              1 // CPU_CLK frequency is 160 MHz (source is PLL_CLK)
 #endif // ESP32C6
 
+#ifdef ESP32H2
+#define PCR_SYSCLK_CONF_REG          (DR_REG_PCR_BASE + 0x10c)
+#define PCR_SOC_CLK_SEL_M            ((PCR_SOC_CLK_SEL_V)<<(PCR_SOC_CLK_SEL_S))
+#define PCR_SOC_CLK_SEL_V            0x3
+#define PCR_SOC_CLK_SEL_S            16
+#define PCR_SOC_CLK_MAX              1 // CPU_CLK frequency is 160 MHz (source is PLL_CLK)
+#endif // ESP32C6
+
 /**********************************************************
  * Per-SOC security info buffer size
  */

diff --git a/flasher_stub/stub_flasher.c b/flasher_stub/stub_flasher.c
@@ -63,7 +63,7 @@ static bool can_use_max_cpu_freq()
   #endif
 }
 
-#if ESP32C6
+#if ESP32C6 || ESP32H2
 static uint32_t pcr_sysclk_conf_reg = 0;
 #else
 static uint32_t cpu_per_conf_reg = 0;
@@ -75,7 +75,7 @@ static void set_max_cpu_freq()
   if (can_use_max_cpu_freq())
   {
     /* Set CPU frequency to max. This also increases SPI speed. */
-    #if ESP32C6
+    #if ESP32C6 || ESP32H2
     pcr_sysclk_conf_reg = READ_REG(PCR_SYSCLK_CONF_REG);
     WRITE_REG(PCR_SYSCLK_CONF_REG, (pcr_sysclk_conf_reg & ~PCR_SOC_CLK_SEL_M) | (PCR_SOC_CLK_MAX << PCR_SOC_CLK_SEL_S));
     #else
@@ -92,7 +92,7 @@ static void reset_cpu_freq()
 {
   /* Restore saved sysclk_conf and cpu_per_conf registers.
      Use only if set_max_cpu_freq() has been called. */
-  #if ESP32C6
+  #if ESP32C6 || ESP32H2
   if (can_use_max_cpu_freq() && pcr_sysclk_conf_reg != 0)
   {
     WRITE_REG(PCR_SYSCLK_CONF_REG, (READ_REG(PCR_SYSCLK_CONF_REG) & ~PCR_SOC_CLK_SEL_M) | (pcr_sysclk_conf_reg & PCR_SOC_CLK_SEL_M));