Incorrect ethernet initialization sequence. PHY: LAN8720 (IDFGH-5035)

[Sejny]

I found bug in IDF ethernet driver. PHY LAN8720 initialization sequence is not correct. PHY clock is supplied by ESP32 (ETH_CLOCK_GPIO17_OUT), tested on ESP-IDF Release v3.3.5

ESP must deliver PHY clock approx 40 clock cycles before PHY reset go HIGH.

Microchip note in LAN8720 datasheet:

Measured on real setup:

Iam not skilled for repair this self :(

[suda-morris]

Hi @Sejny May I ask how you do the PHY hardware reset in your code? In IDF 3.3, we didn't provide a "reset GPIO" configuration in the ethernet driver.

[Alvin1Zhang]

Thanks for reporting, fix is available fc60e09, feel free to reopen.