esp_system: fix garbled UART output on startup on esp32s2

Closes #9168
espressif · Jun 29, 2022 · 74e9376 · 74e9376
1 parent 6c5fb29
commit 74e9376
Showing 1 changed file with 6 additions and 0 deletions.
diff --git a/components/esp_system/port/soc/esp32s2/clk.c b/components/esp_system/port/soc/esp32s2/clk.c
@@ -71,6 +71,12 @@ static void select_rtc_slow_clk(slow_clk_sel_t slow_clk);
     soc_reset_reason_t rst_reas = esp_rom_get_reset_reason(0);
     if (rst_reas == RESET_REASON_CHIP_POWER_ON) {
         cfg.cali_ocode = 1;
+        /* Ocode calibration will switch to XTAL frequency, need to wait for UART FIFO
+         * to be empty, to avoid garbled output.
+         */
+        if (CONFIG_ESP_CONSOLE_UART_NUM >= 0) {
+            esp_rom_uart_tx_wait_idle(CONFIG_ESP_CONSOLE_UART_NUM);
+        }
     }
     rtc_init(cfg);